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| 型號： | AD8158ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX QUAD 2X1 100LFCSP |
| 產(chǎn)品變化通告： | AD8158 Change of Default Settings 13/Aug/2009 |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 4 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 3.6 V |
| 電流 - 電源： | 780mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 100ピンLFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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AD8158
Rev. B | Page 20 of 36
Lane Disables
By default, the receivers and transmitters enable in an on-demand
fashion according to the state of the SEL[3:0], LB_[A:C], and
BICAST pins or to the state of the equivalent registers in serial
control mode. Register 0x40, Register 0x80, and Register 0xC0
implement per-lane disables for the receivers, and Register 0x48,
Register 0x88, and Register 0xC8 implement per-lane transmit-
ter disables. These disables override the default settings. Each
bit in the register is named for the lane and function it disables.
For example, RXDIS B0 disables the receiver on Lane 0 of Port B
whereas TXDIS C1 disables the Lane 1 transmitter of Port C
(see Table 11).
Lane Inversion: P/N Swap
The receiver P/N swap function is a convenience intended to
allow the user to implement the equivalent of a board-level
routing crossover in a much smaller area while eliminating vias
(impedance discontinuities) that compromise the high frequency
integrity of the signal path. Using this feature to correct an
inversion downstream of the receiver may require the user to be
aware of the sign of the data when switching connectivity (the
mux/demux path). The feature is available on a per-lane setting
through Register 0x44, Register 0x84, and Register 0xC4.
Setting the bit true flips the sign sense of the P and N inputs for
the associated lane. The default setting is 0 (no inversion).
Table 11. Per-Lane Disables
Address
Port
Default
Register Name
Bit
Bit Name
Functionality Description
0x40
Port A
0x00
RX[A/B/C] disable
7:4
Reserved
Set to 0
0x80
Port B
0x00
3
RXDIS [A/B/C]3
0: RX Port [A/B/C], Lane 3, enabled
1: RX Port [A/B/C], Lane 3, disabled
0xC0
Port C
0x00
2
RXDIS [A/B/C]2
0: RX Port [A/B/C], Lane 2, enabled
1: RX Port [A/B/C], Lane 2, disabled
1
RXDIS [A/B/C]1
0: RX Port [A/B/C], Lane 1, enabled
1: RX Port [A/B/C], Lane 1, disabled
0
RXDIS [A/B/C]0
0: RX Port [A/B/C], Lane 0, enabled
1: RX Port [A/B/C], Lane 0, disabled
0x48
Port A
0x00
TX[A/B/C] disable
7:4
Reserved
Set to 0
0x88
Port B
0x00
3
TXDIS [A/B/C]3
0: TX Port [A/B/C], Lane 3 enabled
1: TX Port [A/B/C], Lane 3 disabled
0xC8
Port C
0x00
2
TXDIS [A/B/C]2
0: TX Port [A/B/C], Lane 2 enabled
1: TX Port [A/B/C], Lane 2 disabled
1
TXDIS [A/B/C]1
0: TX Port [A/B/C], Lane 1, enabled
1: TX Port [A/B/C], Lane 1, disabled
0
TXDIS [A/B/C]0
0: TX Port [A/B/C], Lane 0, enabled
1: TX Port [A/B/C], Lane 0, disabled
Table 12. Lane Inversion
Address
Port
Default
Register Name
Bit
Bit Name
Functionality Description
0x44
Port A
0x00
RX[A/B/C] P/N swap
7:4
Reserved
Set to 0
0x84
Port B
0x00
3
PN[A/B/C]3
0: Lane 3 noninverted
1: Lane 3 inverted
0xC4
Port C
0x00
2
PN[A/B/C]2
0: Lane 2 noninverted
1: Lane 2 inverted
1
PN[A/B/C]1
0: Lane 1, noninverted
1: Lane 1, inverted
0
PN[A/B/C]0
0: Lane 0, noninverted
1: Lane 0, inverted
Table 13. Port-Level EQ Setting
Address
Port
Default
Register Name
Bit
Bit Name
Functionality Description
0x41
Port A
0x00
RX[A/B/C] EQ setting
7:4
Reserved
Set to 0
0x81
Port B
0x00
3:0
[A/B/C]EQ[3:0]
0xC1
Port C
0x00
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