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| 型號： | AD8158ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/36頁 |
| 文件大小： | 0K |
| 描述： | IC MUX/DEMUX QUAD 2X1 100LFCSP |
| 產(chǎn)品變化通告： | AD8158 Change of Default Settings 13/Aug/2009 |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 多路復用器/多路分解器 |
| 電路： | 4 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 3.6 V |
| 電流 - 電源： | 780mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 100ピンLFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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AD8158
Rev. B | Page 22 of 36
TRANSMITTERS
The AD8158 transmitter offers programmable preemphasis,
programmable output levels, output disable, and transmit
squelch. The SEL4G pin lets the user lower the transmitter
frequency of maximum boost from 3.25 GHz to 2.0 GHz,
allowing the AD8158 to offer exceptional transmit channel
compensation for legacy applications (4.5 Gbps and slower).
VCC
VTTO
OP_xx
ON_xx
VEE
Q1
Q2
RP
RTERM
RN
RTERM
V3
VC
V1
VN
V2
VP
IT
IDC + IPE
ON-CHIP TERMINATION
ESD
06
64
6-
1
39
Figure 39. Simplified Transmitter Structure
Output Level Programming and Output Structure
The output level of the transmitter of each lane is independently
programmable. In pin control mode, a default output amplitude
of 800 mV p-p diff (±400 mV diff) is delivered (see Table 17).
Register-based control allows the user to set the transmitter
output levels on a per-port or per-lane basis to four predefined
levels. Port-level programming overwrites lane-level configuration.
The ALEV, BLEV, and CLEV bits in Register 0x49, Register 0x89,
and Register 0xC9, respectively, are used to set the output levels
for all transmitters. The A[3:0]OLEV[1:0], B[3:0]OLEV[1:0],
and C[3:0]OLEV[1:0] bits in Register 0x4C, Register 0x8C, and
Register 0xCC allow per-lane settings (see Table 22).
Table 17. Predefined Output Levels
[A/B/C][3:0]OLEV[1]
[A/B/C][3:0]OLEV[0]
Output Level
0
±200 mV diff
0
1
±300 mV diff
1
0
±400 mV diff
(default)
1
± 600 mV diff
Note that the choice of output level influences the output
common-mode level. A 600 mV diff output level with a full PE
range requires a supply and output termination voltage of 2.5 V
or higher (VTTO, VCC ≥ 2.5 V).
Preemphasis
Transmitter preemphasis levels can be set by pin control or
through the control registers. Pin control allows two settings of
PE, 0 dB and 6 dB. The control registers provide seven levels of
PE. Note that a larger range of boost settings is available for lower
output levels. Note that toggle pin control of PE is limited to the
400 mV diff output level settings. Table 18 lists the available
preemphasis settings for each output level.
Preemphasis can be programmed per port or per lane. Register
0x49, Register 0x89, and Register 0xC9 set all outputs in a port
at once. Registers 0x4A, 0x8A, and 0xCA allow setting PE on a
per-lane basis. The following equation sets preemphasis boost:
)
1
(
log
20
]
[
10
DC
SW
DC
SW
PE
SW
V
dB
Gain
+
×
=
(1)
Table 18. Setting Transmitter Preemphasis
Output Level
(mV diff)
Pin
PE_[A/B/C]
Bit
PE[2:0]
PE Boost
(%)
PE Boost
(dB)
200
N/A
000
0
200
N/A
001
50
3.52
200
N/A
010
100
6.02
200
N/A
011
150
7.96
200
N/A
100
200
9.54
200
N/A
101
250
10.88
200
N/A
110
300
12.04
300
N/A
000
0
300
N/A
001
33
2.5
300
N/A
010
67
4.44
300
N/A
011
100
6.02
300
N/A
100
133
7.36
300
N/A
101
167
8.52
300
N/A
110
200
9.54
400
0
000
0
400
N/A
001
25
1.94
400
N/A
010
50
3.52
400
N/A
011
75
4.86
400
1
100
6.02
400
N/A
101
125
7.04
400
N/A
110
150
7.96
600
N/A
000
0
600
N/A
001
17
1.34
600
N/A
010
33
2.5
600
N/A
011
50
3.52
600
N/A
100
67
4.44
600
N/A
101
83
5.26
600
N/A
110
100
6.02
Squelch and Disable
Each transmitter is equipped with disable and squelch controls.
Disable is a full power-down state: the transmitter current is
reduced to zero and the output pins pull up to VTTO, but there
is a delay of approximately 1 μs associated with reenabling
the transmitter. Squelch keeps the output current enabled such
that both output pins are at the output common-mode voltage.
The transmitter recovers from squelch in less than 64 ns.
Speed Select
The SEL4G pin lets the user lower the transmitter frequency of
maximum boost from 3.25 GHz to 2.0 GHz, allowing the
AD8158 to offer exceptional transmit channel compensation for
legacy applications (4.5 Gbps and slower). SEL4G = 1 lowers the
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