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參數(shù)資料
| 型號： | AD7870AJN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 250K |
| 代理商： | AD7870AJN |
AD7870A
–7–
REV. 0
Figure 6. Full-Scale Adjust Circuit
Positive Full-Scale Adjust
Apply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V
1
. Adjust
R2 until the ADC output code flickers between 0111 1111
1110 and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –2.9993 V (–FS/2 +1/ 2 LSB) at V
1
and
adjust R2 until the ADC output code flickers between
1000 0000 0000 and 1000 0000 0001.
UNIPOLAR OPERATION
A typical unipolar circuit is shown in Figure 7. The AD7870A
REF OUT is used to offset the analog input by 3 V. The ana-
log input range is determined by the ratio of R3 to R4. The
minimum range with which the circuit will work is 0 V to +3 V
(R3 = 0, R4 = O/C). The resistor values are given in Figure 7
for input ranges of 0 V to +5 V and 0 V to +10 V. R5 and R6
are included for offset and full-scale adjust only and should be
omitted if adjustment is not required.
Figure 7. Unipolar Circuit
The ideal input/output transfer function is shown in Figure 8.
The output can be converted to natural binary by inverting the
MSB.
Figure 8. Unipolar Transfer Function
UNIPOLAR OFFSET AND FULL-SCALE ADJUSTMENT
When absolute accuracy is required, offset and full-scale error
can be adjusted to zero. Offset must be adjusted before full
scale. This is achieved by applying an input voltage of (1/2 LSB)
to V
l
and adjust R6 until the ADC output code flickers between
1000 0000 0000 and 1000 0000 0001. For full-scale adjust-
ment, apply an input voltage of (FS–3/2 LSBs) to V
l
and adjust
R5 until the output code flickers between 0111 1111 1110 and
0111 11111111.
TIMING AND CONTROL
The AD7870A is capable of one basic interfacing mode. In this
mode (Mode 1), the
CONVST
line is used to start conversion
and drive the track/hold into its hold mode. At the end of con-
version the track/hold returns to its tracking mode. It is princi-
pally intended for digital signal processing and other applications
where precise sampling in time is required. In these applica-
tions, it is important that the signal sampling occurs at exactly
equal intervals to minimize errors due to sampling uncertainty
or jitter. For these cases, the
CONVST
line is driven by a timer
or some precise clock source.
DATA OUTPUT FORMATS
The AD7870A offers a choice of three data output formats, one
serial and two parallel. The parallel data formats are a single,
12-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the
12/
8
/CLK input. A logic high on this pin selects the 12-bit par-
allel output format only. A logic low or –5 V applied to this pin
allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in paral-
lel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
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| AD7870AQ | 功能描述:IC ADC 12BIT SAMPLING 3V 24-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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