參數(shù)資料
型號： AD7870AJN
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù)： 3/12頁
文件大小： 250K
代理商： AD7870AJN
AD7870A
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V. See Figures 9 and 10.)
Limit at T
MIN
, T
MAX
(J Version)
Parameter
Units
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
63
t
74
50
0
60
0
70
57
5
50
0
0
100
370
135
100
10
100
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
CONVST
Pulse Width
CS
to
RD
Setup Time (Mode 1)
RD
Pulse Width
CS
to
RD
Hold Time (Mode 1)
RD
to
INT
Delay
Data Access Time after
RD
Bus Relinquish Time after
RD
t
8
t
9
t
t
10
t
126
t
13
t
14
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
SSTRB
to SCLK Falling Edge Setup Time
SCLK Cycle Time
SCLK to Valid Data Delay. C
L
= 35 pF
SCLK Rising Edge to
SSTRB
Bus Relinquish Time after SCLK
NOTES
1
Timing specifications in
bold print
are 100% production tested. All other times are sample tested at +25
°
C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Serial timing is measured with a 4.7 k
pull-up resistor on SDATA and
SSTRB
and a 2 k
pull-up on SCLK. The capacitance on all three outputs is 35 pF.
3
t
6
is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t
7
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
5
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6
t
6
SDATA will drive higher capacitive loads but this will add to t
12
since it increases the external RC time constant (4.7 k
i
C
L
) and hence the time to reach 2.4 V.
Specifications subject to change without notice.
a. High-Z to V
OH
b. High-Z to V
OL
Figure 1. Load Circuits for Access Time
a. V
OH
to High-Z
b. V
OL
to High-Z
Figure 2. Load Circuits for Output Float Delay
相關(guān)PDF資料
PDF描述
AD7874AN LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
AD7874AQ LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
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AD7874BN 10-Bit, 60 MSPS ADC SE/Diff, Int/Ext Ref., program. input range w/Pwrdn and comp. to ADS822/3/5/8 28-SSOP -40 to 85
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