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AD7869
TIMNGSPECIFICATIONS
1, 2
–4–
REV. A
Limit at T
MIN
, T
MAX
(All Versions)
Parameter
Units
Conditions/Comments
ADC T IMING
t
1
t
23
t
3
t
4
50
440
100
20
100
155
4
100
2 RCLK + 200 to
3 RCLK + 200
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
CONVST
Pulse Width
RCLK Cycle T ime, Internal Clock
RFS
to RCLK Falling Edge Setup T ime
RCLK Rising Edge to
RFS
t
54
t
6
RCLK to Valid Data Delay, C
L
= 35 pF
Bus Relinquish T ime after RCLK
t
135
CONVST
to
RFS
Delay
DAC T IMING
t
7
t
8
t
9
t
10
t
11
t
l2
50
75
150
30
75
40
ns min
ns min
ns min
ns min
ns min
ns min
TFS
to T CLK Falling Edge
T CLK Falling Edge to
TFS
T CLK Cycle T ime
Data Valid to T CLK Setup T ime
Data Valid to T CLK Hold T ime
LDAC
Pulse Width
NOT ES
1
T iming specifications are sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2
Serial timing is measured with a 4.7 k
pull-up resistor on DR and
RFS
and a 2 k
pull-up resistor on RCLK . T he capacitance on all three outputs is 35 pF.
3
When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.
4
DR will drive higher capacitance loads but this will add to t
since it increases the external RC time constant (4.7 k
//C
L
) and hence the time to reach 2.4 V.
5
T ime 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6
T CLK mark/space ratio is 40/60 to 60/40.
ABSOLUT E MAX IMUM RAT INGS*
(T
A
= + 25
°
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
V
IN
to AGND . . . . . . . . . . . . . . . . V
SS
–0.3 V to V
DD
+ 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating T emperature Range
J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300
°
C
Power Dissipation (Any Package) to +75
°
C . . . . . . . 1000 mW
Derates above +75
°
C by . . . . . . . . . . . . . . . . . . . . 10 mW/
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDE RING GUIDE
Signal-
to-Noise
Ratio (SNR)
T emperature
Range
Relative
Accuracy
Package
Option*
Model
AD7869JN
AD7869JR
AD7869AQ
0
°
C to +70
°
C
0
°
C to +70
°
C
–40
°
C to +85
°
C
78 dB
78 dB
77 dB
±
2 LSB max
±
2 LSB max
±
2 LSB max
N-24
R-28
Q-24
*N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V)