參數(shù)資料
型號(hào)： AD7869
廠商： Analog Devices, Inc.
英文描述： Complete 14-bit I/O System Containing a DAC and a ADC(完備的14位I/O系統(tǒng)（包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器）)
中文描述： 完整的14位I / O系統(tǒng)含的DAC和ADC的（完備的14位的I / O系統(tǒng)（包含一個(gè)的A / D轉(zhuǎn)換器和一個(gè)的D / A轉(zhuǎn)換器））
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 308K
代理商： AD7869
AD7869
–10–
REV. A
Performance versus Frequency
T he typical performance plots of Figures 14 and 15 show the
AD7869 DAC performance over a wide range of input frequen-
cies at an update rate of 83 kHz. T he plot of Figure 14 is with-
out a sample-and-hold on the DAC output while the plot of
Figure 15 is generated with a sample-and-hold on the output.
Figure 14. DAC Performance vs. Frequency (No
Sample-and-Hold)
Figure 15. DAC Performance vs. Frequency (Sample-and-
Hold)
T he digitizer sampling is synchronized with the DAC update
rate to ease FFT calculations. T he digitizer samples the DAC
output after the output has settled to its new value. T herefore, if
the digitizer were to directly sample the output, it would effec-
tively be sampling a dc value each time. As a result, the dynamic
performance of the DAC would not be measured correctly. Us-
ing the digitizer directly on the DAC output would give better
results than the actual performance of the DAC. Using a filter
between the DAC and the digitizer means that the digitizer
samples a continuously moving signal, and the true dynamic
performance of the AD7869 DAC output is measured.
Figure 12 shows a typical 2048 point Fast Fourier T ransform
plot for the AD7869 DAC with an update rate of 83 kHz and an
output frequency of 1 kHz. T he SNR obtained from the graph is
82 dBs.
Figure 12. DAC FFT Plot
Some applications will require improved performance versus fre-
quency from the AD7869 DAC. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 13 will
extend the very good performance of the DAC to 20 kHz. Other
applications will already have an inherent sample-and-hold
function following the AD7869 DAC output. An example of
this type of application is driving a switched capacitor filter
where the updating of the DAC is synchronized with the
switched capacitor filter. T his inherent sample-and-hold func-
tion also extends the frequency range performance.
AD7869*
LDAC
LDAC
V
OUT
Q
ADG201HS
S1
D1
IN1
AD711
*ADDITIONAL PINS OMITTED FOR CLARITY
R2
2k2
C9
330pF
1
μ
s
ONE SHOT
DELAY
R1
2k2
Figure 13. DAC Sample-and-Hold Circuit
相關(guān)PDF資料
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