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AD7750
–4–
REV. 0
PIN FUNCT ION DE SCRIPT IONS
Pin
No.
1
2
Mnemonic
V
DD
G1
Descriptions
Power Supply Pin, 5 V nominal
±
5% for specifications.
Gain Select, Digital Input. T his input selects the gain for the Channel 1 differential input. When G1 is
low, the gain is 1 and when G1 is high, the gain is 16. See Analog Inputs section.
Channel 1 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input
signal ranges. Channel 1 has selectable gains of 1 and 16. T he absolute maximum rating is
±
6 V for each
pin. T he recommended clamp voltage for external protection circuitry is
±
5 V.
T he Analog Ground reference level for Channels 1 and 2 differential input voltages. Absolute voltage
range relative to DGND pin is –20 mV to +20 mV. T he Analog Ground of the PCB should be connected
to digital ground by connecting the AGND pin and DGND pin together at the DGND pin.
Channel 2 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input
signal ranges. Channel 2 has a fixed gain of 2. T he absolute maximum rating is
±
6 V for each pin. T he
recommended clamp voltage for external protection circuitry is
±
5 V.
Internal Reference Output. T he AD7750 can use either its own internal 2.5 V reference or an external
reference. For operation with the internal reference this pin should be connected to the REFIN pin.
Reference Input. T he AD7750 can use either its own internal 2.5 V reference or an external reference.
For operation with an external reference, a 2.5 V
±
8%, reference should be applied at this pin. For op-
eration with an internal reference, the REFOUT pin should be connected to this input. For both internal
or external reference connections, an input filtering capacitor should be connected between the REFIN
pin and Analog Ground.
T he Ground and Substrate Supply Pin, 0 V. T his is the reference ground for the digital inputs and out-
puts. T hese pins should have their own ground return on the PCB, which is joined to the Analog Ground
reference at one point, i.e., the DGND pin.
Frequency Select, Digital Input. T his input, along with S1 and S2, selects the operating mode of the
AD7750—see T able I.
Mode Selection, Digital Inputs. T hese pins, along with FS, select the operating mode of the AD7750—
see T able I.
High-Pass Filter Control Digital Input. When this pin is high, the high-pass filter is switched into the
signal path of Channel 1. When this pin is low, the high-pass filter is removed. Note when the filter is off
there is a fixed time delay between channels; this is explained in the Functional Description section.
An external clock can be provided at this pin. Alternatively, a crystal can be connected across CLK IN
and CLK OUT for the clock source. T he clock frequency is 3.58 MHz for specified operation.
When using a crystal, it must be connected across CLK IN and CLK OUT . T he CLK OUT can drive
only one CMOS load when CLK IN is driven externally.
Reverse Polarity, Digital Output. T his output becomes active high when the polarity of the signal on
Channel 1 is reversed. T his output is reset to zero at power-up. T his output becomes active only when
there is a pulse output on F1 or F2. See Reverse Polarity Indicator section.
High-Speed Frequency Output. T his is also a fixed-width pulse stream that is synchronized to the
AD7750 CLK IN. T he frequency is proportional to the product of Channel 1 and Channel 2 or the signal
on either channel, depending on the operating mode—see T able I. T he output format is an active high
pulse approximately 90 ms wide—see Digital-to-Frequency Conversion section.
Frequency Outputs. F1 and F2
provide fixed-width pulse streams that are synchronized to the AD7750
CLK IN. T he frequency is proportional to the product of Channel 1 and Channel 2—see T able I. T he
output format is an active low pulse approximately 275 ms wide—see Digital-to-Frequency Conver-
sion section.
3, 4
V
1(+)
, V
1(–)
5
AGND
6, 7
V
2(+)
, V
2(–)
8
REFOUT
9
REFIN
10
DGND
11
FS
13, 12
S1, S2
14
ACDC
15
CLK IN
16
CLK OUT
17
REVP
18
F
OUT
20, 19
F1, F2