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參數(shù)資料
| 型號： | AD7750AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Product-to-Frequency Converter |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 195K |
| 代理商： | AD7750AN |
AD7750
–10–
REV. 0
Maximum Output Frequencies
T able II shows the maximum output frequencies of F
OUT
and
F1, F2 for the various operating modes of the AD7750. T he
table shows the maximum output frequencies for dc and ac
input signals on V
1
and V
2
. When an ac signal (sinusoidal) is
applied to V
1
and V
2
the AD7750 produces an output frequency
which is proportional to the product of the rms value of these
inputs. If two ac signals with peak differential values of V
1MAX
and V
2MAX
are applied to Channels 1 and 2, respectively, then
the output frequency is proportional to V
1MAX
/sqrt(2)
×
V
2MAX
/
sqrt(2) = (V
1MAX
×
V
2MAX
)/2. If V
1MAX
and V
2MAX
are also the
maximum dc input voltages then the maximum output frequen-
cies for ac signals will always be half that of dc input signals.
Example calculation of F1, F2 max for Mode 2 and Gain = 1.
T he maximum input voltage (dc) on Channel 1 is 2 V (V
1+
=
+1 V, V
1–
= –1 V)—see Analog Inputs section. T he maximum
input voltage on Channel 2 is 1 V. Using the transfer function:
k
= (1.32
×
V
1
×
V
2
×
Gain
)/
V
REF
k
= 0.4224
F
1,
F
2 =
k
.6.8
Hz
= 2.9
Hz
2
FUNCT IONAL DE SCRIPT ION
T he AD7750 combines two analog-to-digital converters, a digi-
tal multiplier, digital filters and a digital-to-frequency (DT F)
converter onto one low cost integrated circuit. T he AD7750 is
fabricated on a double poly CMOS process (0.6
μ
) and retains
its high accuracy by performing all multiplications and manipu-
lations in the digital domain. T he schematic in Figure 15 shows
an equivalent circuit for the AD7750 signal processing chain.
T he first thing to notice is that the analog signals are first con-
verted to digital signals by the two second-order sigma-delta
modulators. All subsequent signal processing is carried out in
the digital domain. T he main source of errors in an application
is therefore in the analog-to-digital conversion process. For this
reason great care must be taken when interfacing the analog
inputs of the AD7750 to the transducer. T his is discussed in the
Applications section.
HPF in Channel 1
T o remove any dc offset that may be present at the output
modulator 1, a user selectable high-pass IIR filter (Pin ACDC)
can be introduced into the signal path. T his HPF is necessary
when carrying out power measurements. However, this HPF
has an associated phase lead given by 90
°
–tan
–1
(f/2.25). Figure
16 shows the transfer function of the HPF in Channel 1. T he
Phase lead is 2.58
°
at 50 Hz. In order to equalize the phase
difference between the two channels a fixed time delay is intro-
duced. T he time delay is set at 143
μ
s, which is equivalent to a
phase lag of –2.58
°
at 50 Hz. T hus the cumulative phase shift
through Channel 1 is 0
°
.
Because the time delay is fixed, external phase compensation
circuitry will be required if the line frequency differs from
50 Hz. For example with a line frequency of 60 Hz the phase
lead due to the HPF is 2.148
°
and the phase lag due to the fixed
time delay is 3.1
°
. T his means there is a net phase lag in Chan-
nel 1 of 0.952
°
. T his phase lag in Channel 1 can be compen-
sated for by using a phase lag compensation circuit like the
one shown in Figure 17. T he phase lag compensation is placed
on Channel 2 (voltage channel) to equalize the channels. T he
antialiasing filter associated with Channel 1 (see Applications
section) produces a phase lag of 0.6
°
at 50 Hz; therefore, to
equalize the channels, a net phase lag of (0.6
°
+ 0.952
°
) 1.552
°
should be in place on Channel 2. T he gain trim resistor VR1
(100
) produces a phase lag variation of 1.4
°
to 1.5
°
with VR2
= 0
. VR2 can add an additional 0.1
°
phase lag (VR2 = 200
).
V2
(+)
FOUR QUADRANT MULTIPLICATION
(SIGN AND MAGNITUDE)
TWO QUADRANT MULTIPLICATION
( MAGNITUDE ONLY)
V2
(+)
(1.32
3
V1
3
V2
3
GAIN)
VREF2
K =
V2(–)
0
V2(–)
k
3
F
MAX
(+)
F
MAX
+ k
3
F
MAX
(+)
F
MAX
– k
3
F
MAX
(–)
k
3
F
MAX
(+)
F
MAX
+ k
3
F
MAX
(+)
F
MAX
_ k
3
F
MAX
(–)
k
3
F
MAX
(+)
k
3
F
MAX
(+)
V1(–)
V1(+)
V1(–)
V1(+)
Figure 14. Transfer Functions (Four and Two Quadrant Multiplication)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7750AN | 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NW)) |
| AD7750AR | 制造商:Rochester Electronics LLC 功能描述:PRODUCT TO FREQUENCY CONVERTER I.C. - Bulk |
| AD7750AR-REEL | 制造商:Analog Devices 功能描述: |
| AD7751 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Energy Metering IC With On-Chip Fault Detection |
| AD7751AAN | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:PRODUCT TO FREQUENCY CONV - Bulk |
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