參數(shù)資料
型號(hào)： AD7738
廠商： Analog Devices, Inc.
英文描述： 8-Channel, High Throughput,
中文描述： 8通道，高通量，
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 407K
代理商： AD7738
REV. 0
–24–
AD7738
-
CHANNEL 1
SCALING
TIME
SAMPLING
TIME
+CHANNEL 1
SAMPLING
TIME
SETTLING
TIME
MULTIPLEXER
-
CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
+CHANNEL 2
Figure 14. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
SCALING
TIME
+CHANNEL 1
SAMPLING
TIME
+CHANNEL 0
+CHANNEL 2
SETTLING
TIME
CONVERSION TIME
MULTIPLEXER
RDY
Figure 15. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
MULTIPLEXER
AIN(+)
AIN(–)
+
DIGITAL
FILTER
MUXOUT
ADCIN
-
MODULATOR
BUFFER
-
SCALING
ARITHMETIC
(CALIBRATIONS)
CHOP
CHOP
f
MCLK
/2
f
MCLK
/2
DIGITAL
INTERFACE
OUTPUT DATA
AT THE SELECTED
DATA RATE
Figure 13. Channel Signal Chain Diagram with Chopping Enabled
Multiplexer, Conversion, and Data Output Timing
The specified “Conversion Time” includes one or two “Settling”
and “Sampling” periods and a “Scaling” time.
With chopping enabled (Figure 14), a conversion cycle starts
with a “Settling” time of 43 or 44 MCLK cycles (~7
μ
s with
6.144 MHz MCLK) to allow the circuits following the multiplexer
to settle. Then the sigma-delta modulator samples the analog
signals, and the digital filter processes the digital data stream.
The “Sampling” time depends on FW, i.e., on the Channel
Conversion Time register contents. After another “Settling” of
42 MCLK cycles (~6.8
μ
s), the “Sampling” time is repeated
with a reversed (chopped) analog input signal. Then, during the
“Scaling” time of 163 MCLK cycles (~26.5
μ
s), the two results
from the digital filter are averaged, scaled using the Calibration
registers, and written into the Channel Data register.
With chopping disabled (Figure 15), there is only one “Sampling”
time preceded by a “Settling” time of 43 or 44 MCLK cycles
and followed by a “Scaling” time of 163 MCLK cycles.
The
RDY
pin goes high during the “Scaling time” regardless of
its previous state. The relevant RDY bit is set in the ADC Sta-
tus register, and in the Channel Status register the
RDY
pin
goes low when the Channel Data register is updated and the
channel conversion cycle is finished. If in Continuous Conversion
mode, the part will automatically continue with a conversion
cycle on the next enabled channel.
Note, that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and effec-
tive per channel data rate depends on all enabled channel settings.
Frequency Response
The sigma-delta modulator runs at 1/2 of MCLK frequency,
which is effectively the sampling frequency. Therefore, the
Nyquist frequency is 1/4 of the MCLK frequency. The digital
filter, in association with the modulator, features frequency
response of a first order low-pass filter. The –3 dB point is close
to the frequency of 1/Channel Conversion Time. The roll-off is
–20 dB/dec up to the Nyquist frequency. If chopping is enabled,
the input signal is resampled by chopping. Therefore, the over-
all frequency response features notches close to the frequency of
1/Channel Conversion Time. The top envelope is again the
ADC response of –20 dB/dec.
The typical frequency response plots are in Figure 16. The plots
are normalized to 1/Channel Conversion Time.
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