參數(shù)資料
型號(hào): AD7738
廠商: Analog Devices, Inc.
英文描述: 8-Channel, High Throughput,
中文描述: 8通道,高通量,
文件頁(yè)數(shù): 13/28頁(yè)
文件大?。?/td> 407K
代理商: AD7738
REV. 0
AD7738
–13–
REGISTER DESCRIPTION
The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are
specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communi
cation
register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register
will be subsequently read or written.
Communications Register
8 Bits, Write-Only Register, Address 00h
All communications to the part must start with a write operation to the Communications register. The data written to the Commu-
nications register determines whether the subsequent operation will be a read or write and to which register this operation will be
directly placed.
The digital interface defaults to expect write operation to the Communication register after power on, after reset, or
after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset
by writing at least 32 serial clock cycles with DIN high and
CS
low (Note that all of the parts including modulator, filter, interface
and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or
with the DUMP bit and “24/16” bit in the Mode register set.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
0
R/
W
6-Bit Register Address
Bit
Mnemonic
Description
7
6
0
R/
W
This bit must be zero for proper operation.
A zero in this bit indicates that the next operation will be a write to a specified register.
A one in this bit indicates that the next operation will be a read from a specified register.
Address specifying to which register the read or write operation will be directed.
For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number.
When the subsequent operation writes to the Mode register, then the three LSBs specify the channel
selected for operation determined by the Mode register value. See Table X.
(The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.)
5–0
Address
Table X.
Bit 2
Bit 1
Bit 0
Channel
Single Input
Differential Input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN0–AIN1
AIN2–AIN3
AIN4–AIN5
AIN6–AIN7
AIN0–AIN1
AIN2–AIN3
AIN4–AIN5
AIN6–AIN7
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