- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375238 > AD7710AN (ANALOG DEVICES INC) Signal Conditioning ADC PDF資料下載
參數(shù)資料
| 型號： | AD7710AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MO-095AG, DIP-24 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AD7710AN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. F
–20–
AD7710
Read Operation
Data can be read from either the output register, the control
register or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or from the calibra-
tion registers. With A0 low, data is accessed from the control
register.
The function of the
DRDY
line is dependent only on the output
update rate of the device and the reading of the output data
register.
DRDY
goes low when a new data word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY
line will
remain low. The output register will continue to be updated at
the output update rate but
DRDY
will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data word becomes avail-
able to the output register while data is being read from the
output register,
DRDY
will not indicate this and the new data
word will be lost to the user.
DRDY
is not affected by reading
from the control register or the calibration registers.
Data can only be accessed from the output data register when
DRDY
is low. If
RFS
goes low with
DRDY
high, no data trans-
fer will take place.
DRDY
does not have any effect on reading
data from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7710
in the self-clocking mode. This read operation shows a read
from the AD7710’s output data register. A read from the con-
trol register or calibration registers is similar but in these cases
the
DRDY
line is not related to the read function. Depending
on the output update rate, it can go low at any stage in the con-
trol/calibration register read cycle without affecting the read and
its status should be ignored. A read operation from either the
control or calibration registers must always read 24 bits of data
from the respective register.
Figure 10 shows a read operation from the AD7710. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With
DRDY
low, the
RFS
input
is brought low.
RFS
going low enables the serial clock of the
AD7710 and also places the MSB of the word on the serial data
line. All subsequent data bits are clocked out on a high to low
transition of the serial clock and are valid prior to the following
rising edge of this clock. The final active falling edge of SCLK
clocks out the LSB and this LSB is valid prior to the final active
rising edge of SCLK. Coincident with the next falling edge of
SCLK,
DRDY
is reset high.
DRDY
going high turns off the
SCLK and the SDATA outputs. This means that the data hold
time for the LSB is slightly shorter than for all other bits.
SDATA (O)
SCLK (O)
THREE-STATE
RFS (I)
A0 (I)
t
4
t
5
t
7
t
8
t
10
9
t
DRDY (O)
t
6
t
3
MSB
LSB
t
2
Figure 10. Self-Clocking Mode, Output Data Read Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7710AQ | Signal Conditioning ADC |
| AD7710AR | Signal Conditioning ADC |
| AD7710SQ | Signal Conditioning ADC |
| AD7710* | Signal Conditioning ADC |
| AD7710 | Signal Conditioning ADC(LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7710ANZ | 功能描述:IC ADC SIGNAL CONDITIONING 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7710AQ | 功能描述:IC ADC 24BIT DIFF INP 24-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7710AR | 功能描述:IC ADC 24BIT DIFF INP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7710AR-REEL | 功能描述:IC ADC 24BIT DIFF INP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7710AR-REEL7 | 功能描述:IC ADC 24BIT DIFF INP 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。