參數(shù)資料
型號(hào)： AD7440BRM-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT W/DIFF INP 8-MSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 9.25mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD7440/AD7450A
Rev. C | Page 25 of 28
Thus, the average power dissipated during each cycle with a
throughput rate of 100 kSPS is (2/10) × 4 mW = 0.8 mW.
The connection diagram is shown in Figure 45. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
This is how the power numbers in Figure 44 are calculated.
For throughput rates above 320 kSPS, it is recommended to
reduce the serial clock frequency for best power performance.
CS and, as with all signal processing
applications, equidistant sampling is necessary. However in this
example, the timer interrupt is used to control the sampling rate
of the ADC; under certain conditions, equidistant sampling
may not be achieved.
03051-A
-044
THROUGHPUT (kSPS)
100
0
350
P
O
WE
R
(mW)
0.01
50
100
150
200
250
300
0.1
1
10
VDD = 5V
VDD = 3V
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before starting transmission. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.
Figure 44. Power vs. Throughput Rate for Power-Down Mode
MICROPROCESSOR AND DSP INTERFACING
03051-A
-045
AD7440/
AD7450A*
ADSP-21xx*
SCLK
DR
RFS
TFS
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
The serial interface on the AD7440/AD7450A allows the parts
to be directly connected to many different microprocessors.
This section explains how to interface the AD7440/AD7450A
with some of the more common microcontroller and DSP serial
interface protocols.
AD7440/AD7450A to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7440/AD7450A without any glue logic required.
Figure 45. Interfacing to the ADSP-21xx
The SPORT control register should be set up as follows:
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, then 100.5 SCLKs occur between interrupts
and subsequently between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
Table 7.
Parameter
Description
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right-justify data
SLEN = 1111
16-bit data-words
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
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