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參數(shù)資料
| 型號： | AD73360ASUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG FRONT END 6CH 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 6 |
| 功率（瓦特）： | 80mW |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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REV. A
–5–
AD73360
AD73360A
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
VINH, Input High Voltage
VDD – 0.8
VDD
V
VINL, Input Low Voltage
0
0.8
V
IIH, Input Current
–0.5
A
CIN, Input Capacitance
10
pF
LOGIC OUTPUTS
VOH, Output High Voltage
VDD – 0.4
VDD
V
|IOUT|
≤ 100 A
VOL, Output Low Voltage
0
0.4
V
|IOUT|
≤ 100 A
Three-State Leakage Current
–0.3
A
POWER SUPPLIES
AVDD1, AVDD2
4.5
5.5
V
DVDD
4.5
5.5
V
IDD
8
See Table II
NOTES
1Operating temperature range is as follows: –40
°C to +85°C. Therefore, T
MIN = –40
°C and T
MAX = +85
°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4
× 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table II. Current Summary (AVDD = DVDD = 5.5 V)
Total
Analog
Digital
Current
MCLK
Conditions
Current
(Typ)
SE
ON
Comments
ADCs Only On
16
32
1
YES
REFOUT Disabled
REFCAP Only On
0.8
0
0.8
0
NO
REFOUT Disabled
REFCAP and
REFOUT Only On
3.5
0
3.5
0
NO
All Sections Off
0.1
1.9
2.0
0
YES
MCLK Active Levels Equal to 0 V and DVDD
All Sections Off
0
0.05
0.06
0
NO
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
Table III. Signal Ranges
3 V Power Supply
5 V Power Supply
5VEN = 0
5VEN = 1
VREFCAP
1.25 V
± 10%
1.25 V
2.5 V
VREFOUT
1.25 V
± 10%
1.25 V
2.5 V
ADC
Maximum Input Range at VIN
1.64375 V p-p
3.2875 V p-p
Nominal Reference Level
1.1413 V p-p
2.2823 V p-p
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