參數(shù)資料
型號(hào)： AD73360ASUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/35頁(yè)
文件大?。?/td> 0K
描述： IC ANALOG FRONT END 6CH 44-TQFP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 16
通道數(shù)： 6
功率（瓦特）： 80mW
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.3 V
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
REV. A
AD73360
–29–
APPENDIX B
Programming a Single AD73360 for Mixed Mode Operation
This section describes a typical sequence in programming a
single AD73360 to operate in Mixed Mode. The device is con-
figured in Nonframe Sync Loop-Back (see Figure 14), which
allows the DSP’s Tx Register to determine how many words are
sent to the device during one sample interval. In Nonframe
Sync Loop-Back mode care must be taken when writing to the
AD73360 that an ADC result or register read result contained
in the device’s serial register is not corrupted by a write. The
best way to avoid this is to only write control words when the
AD73360 has no more data to send. This can limit the number
of times a DSP can write to the AD73360 and is dependant on
the SCLK speed and the number of channels powered up. In
this example it is assumed that there are only two channels
powered up and that there is adequate time to transmit data
after the ADC results have been read.
In Step 1, the device has just been reset and the on first output
event the AD73360 presents an invalid ADC sample word
1.
Once this word has been received the DSP can begin transmit-
ting programming information to the AD73360. The first con-
trol word sets the sampling rate at 8 kHz. In Step 2, the DSP
instructs the AD73360 to power up channels 1 and 2 and sets
the gain of each. No data is read from the AD73360 at this
point. Steps 3 and 4 set the reference and places the part into
Mixed Mode. In Steps 5 and 6 valid ADC results are read from
the AD73360 and in Step 7 the DSP sends an instruction to the
AD73360 to change the gain of Channel 1.
NOTE
1This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Register B, as it contains settings for SCLK and
DMCLK rates.
DSP Tx REG
CONTROL WORD
1000 0001 0000 0011
DEVICE 1
ADC WORD 1*
0000 0000 0000 0000
DSP Rx REG
0000 0000 0000 0000
STEP 1
DON'T CARE
DSP Tx REG
CONTROL WORD
1000 0011 1111 1010
DEVICE 1
ADC WORD 1*
1011 1001 0000 0011
DSP Rx REG
0000 0000 0000 0000
STEP 2
DON'T CARE
DSP Tx REG
CONTROL WORD
1000 0010 1110 0000
DEVICE 1
ADC WORD 1*
1011 1011 1111 1010
DSP Rx REG
0000 0000 0000 0000
STEP 3
DON'T CARE
DSP Tx REG
CONTROL WORD
1000 0000 0000 0010
DEVICE 1
ADC WORD 1*
1011 1010 1110 0000
DSP Rx REG
0000 0000 0000 0000
STEP 4
DON'T CARE
DSP Tx REG
CONTROL WORD
0111 1111 1111 1111
DEVICE 1
ADC WORD 1
1000 0000 0000 0000
DSP Rx REG
1000 0000 0000 0000
STEP 5
ADC WORD 1
DSP Tx REG
CONTROL WORD
0111 1111 1111 1111
DEVICE 1
ADC WORD 2
1111 0000 0000 0000
DSP Rx REG
1111 0000 0000 0000
STEP 6
ADC WORD 2
DSP Tx REG
CONTROL WORD
1000 0011 1000 0010
DEVICE 1
INVALID DATA
xxxx xxxx xxxx xxxx
DSP Rx REG
1111 0000 0000 0000
STEP 7
ADC WORD 2
SET 8kHz SAMPLING
POWER UP CHANNEL 1&2 AND SET GAINS
POWER UP REFERENCE
SET MIXED MODE
CHANGE GAIN ON CHANNEL 1
RECEIVE VALID ADC DATA
*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS
Figure 33. Programming a Single AD73360 for Operation in Mixed Mode
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