
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
9
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
E lectrical C haracteristics - P C IC LK /P C IC LK _F
P A RA M E TE R
S Y M B OL
CONDITIONS
M IN
M A X
UNITS
NOTE S
Long A c c urac y
ppm
s ee Tperiod m in-m ax v alues
-100
100
ppm
1,2
33.33M Hz output no s pread
29.99700
30.00300
ns
2
33.33M Hz output s pread
30.08421
30.23459
ns
2
33.33M Hz output no s pread
29.49700
30.50300
ns
2
33.33M Hz output nom inal/s pread
29.56617
30.58421
ns
2
Ris ing E dge S lew Rate
tSLR
M eas ured from 0.8 to 2.0 V
1
4
V /ns
1
Falling E dge S lew Rate
tFLR
M eas ured from 2.0 to 0.8 V
1
4
V /ns
1
P in to P in S k ew
tskew
V T = 1.5 V
250
ps
2
Intential P CI to P CI delay
tskew
V T = 1.5 V
100
200
ps
2
Duty Cy c le
dt1
V T = 1.5 V
45
55
%
2
J itter, Cy c le to c y c le
tjcyc-cyc
V T = 1.5 V
500
ps
2
Tabs
A bs olute m in/m ax period
Cloc k period
Tperiod
E lectrical C h aracteristics - U S B 48MH z
P A RA M E TE R
S Y M B OL
CONDITIONS
M IN
M A X
UNITS
NOTE S
Long A c c urac y
ppm
s ee Tperiod m in-m ax v alues
-100
100
ppm
2,4
Cloc k period
Tperiod
48.00M Hz output nom inal
20.83125
20.83542
ns
2,3
A bs olute m in/m ax period
Tabs
48.00M Hz output nom inal
20.48125
21.18542
ns
2
CLK High Tim e
THIGH
8.216563
11.15198
V
CLK Low tim e
TLOW
7.816563
10.95198
V
Ris ing E dge S lew Rate
tSLR
M eas ured from 0.8 to 2.0 V
1
2
V /ns
1
Falling E dge S lew Rate
tFLR
M eas ured from 2.0 to 0.8 V
1
2
V /ns
1
Duty Cy c le
dt1
V T = 1.5 V
45
55
%
2
J itter, Cy c le to c y c le
tjcyc-cyc
V T = 1.5 V
350
ps
2
E lectrical C h aracteristics - R E F-14.318MH z
P A RA M E TE R
S Y M B OL
CONDITIONS
M IN
M A X
UNITS
Notes
Long A c c urac y
ppm
s ee Tperiod m in-m ax v alues
-100
100
ppm
2, 4
Cloc k period
Tperiod
14.318M Hz output nom inal
69.82033
69.86224
ns
2, 3
A bs olute m in/m ax period
Tabs
14.318M Hz output nom inal
69.83400
70.84800
ns
2
CLK High Tim e
THIG H
29.97543
38.46654
V
CLK Low tim e
TLO W
29.57543
38.26654
V
Ris ing E dge S lew Rate
tS LR
M eas ured from 0.8 to 2.0 V
1
4
V /ns
1
Falling E dge S lew Rate
tFLR
M eas ured from 2.0 to 0.8 V
1
4
V /ns
1
Duty Cy c le
dt1
V T = 1.5 V
45
55
%
2
J itter, Cy c le to c y c le
tjc y c -c y c
V T = 1.5 V
1000
ps
2
1Edge rate in s y s tem is meas ured from 0.8V to 2.0V.
2 Duty c y c le, Peroid and J itter are meas ured w ith res pec t to 1.5V
3 T he av erage period ov er any 1us period of time
4 Us ing frequenc y c ounter with the meas urment interv al equal or greater that 0.15s , target frequenc ies are 14.318180 MHz , 33.333333MHz and 48.000000MHz
N O T ES o n SE o u t p u ts: (u n less o th erw ise n o ted , g u aran teed b y d esig n an d ch aracteriz atio n , n o t 100% tested in p ro d u ctio n ).