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參數(shù)資料
| 型號(hào)： | 9LP525BF-2LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 226K |
| 代理商： | 9LP525BF-2LFT |
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
10
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
266.66
0
1
133.33
0
1
0
200.00
0
1
166.66
1
0
333.33
1
0
1
100.00
1
0
400.00
1
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
Reserved
100.00
33.33 14.318 48.00 96.00
Pin 17 Pin 18
Spread
MHz
%
0
1
100.00 100.00 0.5% Down Spread
SRC clocks from SRC_MAIN
0
1
0
100.00 100.00 0.5% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00 100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00 100.00 1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00 100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00 100.00 2.5% Down Spread
Only SRCCLK1 from PLL3
0
1
N/A
1
0
24.576 24.576
None
24.576Mhz on SE1 and SE2
1
0
1
24.576 98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1
0
98.304 98.304
None
98.304Mhz on SE1 and SE2
1
0
1
27.000 27.000
None
27Mhz on SE1 and SE2
1
0
25.000 25.000
None
25Mhz on SE1 and SE2
1
0
1
N/A
1
0
N/A
1
N/A
B1b1
B1b4 B1b3 B1b2
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6)
Comment
PLL 3 disabled
Table 3: IO_Vout select table
B9b2
B9b1
B9b0
IO_Vout
0
0.3V
0
1
0.4V
0
1
0
0.5V
0
1
0.6V
1
0
0.7V
1
0
1
0.8V
1
0
0.9V
1
1.0V
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