參數(shù)資料
型號(hào)： 9LP525BF-2LFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù)： 18/21頁
文件大?。?/td> 226K
代理商： 9LP525BF-2LFT
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
6
A b so lu te Maxim u m R atin g s - D C P aram eters
P A RA M E TE R
S Y M B O L
CO NDITIO NS
M IN
M A X
UNITS
Notes
M ax im um S upply V oltage
V DDx x x
S upply V oltage
4.6
V
7
M ax im um S upply V oltage
V DDx x x _IO
Low-V oltage Differential I/O S upply
3.8
V
7
M ax im um Input V oltage
V IH
3.3V Inputs
4.6
V
4,5,7
M inim um Input V oltage
V IL
A ny Input
G ND - 0.5
V
4,7
Cas e Tem perature
Tc as e
115
°C
S torage Tem perature
Ts
-
-65
150
°C
4,7
Input E S D protec tion
E S D prot
Hum an B ody M odel
2000
V
6,7
1 G uaranteed by des ign and c harac teriz ation, not 100% tes ted in produc tion.
2 O peration under thes e c onditions is neither im plied, nor guaranteed.
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Ambient Operating Temp
Tambient
-
0
70
°C
Supply Voltage
VDDxxx
Supply Voltage
3.135
3.465
V
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
0.72
0.9
V
10
Input High Voltage
VIHSE
Single-ended 3.3V inputs
2
VDD + 0.3
V
3
Input Low Voltage
VILSE
Single-ended 3.3V inputs
VSS - 0.3
0.8
V
3
Low Threshold Input-
High Voltage
VIH_FS_TEST
3.3 V +/-5%
2
VDD + 0.3
V
8
Low Threshold Input-
FSC = '1' Voltage
VIH_FS_FSC
3.3 V +/-5%
0.7
1.5
V
8
Low Threshold Input-
FSA,FSB = '1' Voltage
VIH_FS_FSAB
3.3 V +/-5%
0.7
VDD+0.3
V
Low Threshold Input-
Low Voltage
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
PCI3/CFG0 Input
VIL_CFGHI
Optional input, 2.75V typ.
2.4
VDD+0.3
V
9
PCI3/CFG0 Input
VIL_CFGMID
Optional input, 1.65V typ.
1.3
2
V
9
PCI3/CFG0 Input
VIL_CFGLO
Optional input, 0.55V typ.
VSS - 0.3
0.9
V
9
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
2
Input Leakage Current
IINRES
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
-200
200
uA
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
2.4
V
1
Output Low Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
0.4
V
1
IDDOP3.3
Full Active, CL = Full load; Idd 3.3V
200
mA
IDDOPIO
Full Active, CL = Full load; IDD IO
70
mA
10
IDDiAMT3.3
M1 mode, 3.3V Rail
80
mA
IDDiAMTIO
M1 Mode, IO Rail
10
mA
IDDPD3.3
Power down mode, 3.3V Rail
5
mA
IDDPDIO
Power down mode, IO Rail
0.1
mA
10
Input Frequency
Fi
VDD = 3.3 V
15
MHz
Pin Inductance
Lpin
7
nH
CIN
Logic Inputs
1.5
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
6
pF
Clk Stabilization
TSTAB
From VDD Power-Up or de-assertion of PD to 1st clock
1.8
ms
Tdrive_CR_off
TDRCROFF
Output stop after CR deasserted
400
ns
Tdrive_CR_on
TDRCRON
Output run after CR asserted
0
us
Tdrive_CPU
TDRSRC
CPU output enable after
PCI_STOP# de-assertion
10
ns
Tfall_SE
TFALL
10
ns
Trise_SE
TRISE
10
ns
SMBus Voltage
VDD
2.7
5.5
V
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.4
V
Current sinking at
VOLSMB = 0.4 V
IPULLUP
SMB Data Pin
4
mA
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
Maximum SMBus Operating Frequency
FSMBUS
100
kHz
Spread Spectrum Modulation
Frequency
fSSMOD
Triangular Modulation
30
33
kHz
iAMT Mode Current
Operating Supply Current
Input Capacitance
Powerdown Current
Fall/rise time of all 3.3V control inputs from 20-80%
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