- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25569 > 9LP525BF-2LFT (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, OTHER CLOCK GENERATOR, PDSO56 PDF資料下載
參數(shù)資料
| 型號： | 9LP525BF-2LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大小： | 226K |
| 代理商： | 9LP525BF-2LFT |
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
7
C lo ck Jitter S p ecs - L o w P o wer D ifferen tial Ou tp u ts
P A RA M E TE R
S Y M B OL
CONDITIONS
M IN
M A X
UNITS
NOTE S
CP U J itter - Cy c le to Cy c le
CP UJ C2C
Differential M eas urem ent
85
ps
1
S RC J itter - Cy c le to Cy c le
S RCJ C2C
Differential M eas urem ent
125
ps
1,2
DOT J itter - Cy c le to Cy c le
DOTJ C2C
Differential M eas urem ent
250
ps
1
1J Itter s pec s are s pec ified as meas ured on a c loc k c harac teriz ation board. Sy s tem des igners need to tak e s pec ial c are not to us e thes e numbers , as the in-s y s tem performanc e will be
s omew hat degraded. T he rec eiv er EMT S (c his pet or C PU ) w ill hav e the rec eiv er jitter s pec s as meas ured ina real s y s tem.
2 Phas e jitter requirement: T he deis gnated G e2 outputs will meet the referenc e c loc k jitter requiremernts from the PCI Ex pres s G en2 Bas e Spec . T he tes t is performed on a c omponnet
tes t board under quiet c ondittions w ith all outputs on. J itter analy s is is performed us ing the s tandardiz ed tool prov ided by the PC I SIG .
N O T ES o n D IF O u tp u t Jitter: (u n less o th erw ise n o ted , g u aran teed b y d esig n an d ch aracteriz atio n , n o t 100% tested in p ro d u ctio n ).
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Rising Edge Slew Rate
tSLR
Averaging on
2.5
4
V/ns
2, 3
Falling Edge Slew Rate
tFLR
Averaging on
2.5
4
V/ns
2, 3
Slew Rate Variation
tSLVAR
Averaging on
20
%
1, 10
Differential Voltage Swing
VSWING
Averaging off
300
mV
2
Crossing Point Voltage
VXABS
Averaging off
300
550
mV
1,4,5
Crossing Point Variation
VXABSVAR
Averaging off
140
mV
1,4,9
Maximum Output Voltage
VHIGH
Averaging off
1150
mV
1,7
Minimum Output Voltage
VLOW
Averaging off
-300
mV
1,8
Duty Cycle
DCYC
Averaging on
45
55
%
2
CPU Skew
CPUSKEW
Averaging on
100
ps
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
3000
ps
1,6,11
1Measurement taken for single ended waveform on a component test board (not in system)
2 Measurement taken from differential waveform on a component test board. (not in system)
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5 Only applies to the differential rising edge (Clock rising, Clock# falling)
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced
modulation by setting C_cross_delta to be smaller than V_Cross absolute.
10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets
Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
7 The max voltage including overshoot.
8 The min voltage including undershoot.
11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1Signal is required to be monotonic in this region.
2 input leakage current does not include inputs with pull-up or pull-down resistors
3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
4 Intentionally blank
5 Maximum VIH is not to exceed VDD
6 Human Body Model
7 Operation under these conditions is neither implied, nor guaranteed.
8 Frequency Select pins which have tri-level input
9 PCI3/CFG0 is optional
10 If present. Not all parts have this feature.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9LPR501SGLF | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPR501SGLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPR501YGT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPR502YGLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 9LPRS365BKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LP525BG-2LF | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LP525BG-2LFT | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPC01781 | 制造商:Denon 功能描述:BUTTON POWERAVR-600 |
| 9LPH02002 | 制造商:Denon 功能描述:DISPLAY SHEETD-C30 |
| 9LPH02481 | 制造商:Denon 功能描述:F/PANELD-C30 |
發(fā)布緊急采購，3分鐘左右您將得到回復。