參數(shù)資料
型號(hào)： 935270030157
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 7/53頁(yè)
文件大?。?/td> 704K
代理商： 935270030157
Philips Semiconductors
SC16C650A
Universal Asynchronous Receiver/Transmitter (UART)
with 32-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 03 — 13 March 2003
15 of 49
9397 750 11207
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.8 DMA operation
The SC16C650A FIFO trigger level provides additional exibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables 6 and 7 show this.
6.9 Sleep mode
The SC16C650A is designed to operate with low power consumption. A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C650A enters the
sleep mode, but resumes normal operation when a start bit is detected, a change of
state on any of the modem input pins RX, RI, CTS, DSR, DCD, or a transmit data is
provided by the user. If the sleep mode is enabled and the SC16C650A is awakened
by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case,
the sleep mode will not be entered while an interrupt(s) is pending. The SC16C650A
will stay in the sleep mode of operation until it is disabled by setting IER[4] to a
logic 0.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and recongured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2-3) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem CTS and DSR inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 7). The CTS, DSR,
DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received data to the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits.
Table 6:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 7:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO
0-to-1 transition when FIFO becomes full
0 = FIFO empty
1-to-0 transition when FIFO goes below trigger level
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