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| 型號： | 935270030157 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 17/53頁 |
| 文件大?。?/td> | 704K |
| 代理商： | 935270030157 |
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Philips Semiconductors
SC16C650A
Universal Asynchronous Receiver/Transmitter (UART)
with 32-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 03 — 13 March 2003
24 of 49
9397 750 11207
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16:
LCR[5] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
0
no parity
0
1
ODD parity
0
1
EVEN parity
101force parity ‘1’
111forced parity ‘0’
Table 17:
LCR[2] stop bit length
LCR[2]
Word length
Stop bit length (bit times)
0
5, 6, 7, 8
1
15
1-1
2
1
6, 7, 8
2
Table 18:
LCR[1-0] word length
LCR[1]
LCR[0]
Word length
005
016
107
118
Table 19:
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
Clock select.
Logic 0 = Divide-by-1. The input clock (crystal or external) is
divided by 16 and then presented to the Programmable Baud Rate
Generator (BGR) without further modication, i.e., divide-by-1
(normal default condition).
Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7]
equals a logic 0, is further divided by four (see also Section 6.7
6
MCR[6]
IR enable.
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
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