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| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 29/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
35 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.4.5
DMA Strobe Timing register (address: 60H)
This 1-byte register controls the strobe timings for the MDMA mode, when the
DMA_MODE bits in the DMA Conguration register have been set to 03H. The bit
allocation is given in Table 37.
Table 36:
DMA Hardware register: bit description
Bit
Symbol
Description
7 to 6
ENDIAN[1:0]
These bits determine whether the data bus is swapped between
internal RAM and the DMA bus: This only applies for modes
GDMA (slave) and MDMA (master):
00H — normal data representation
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01H — swapped data representation
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
02H, 03H — reserved.
Note: while operating with 8 bit data bus, ENDIAN bits should be
always set to 00H.
5
EOT_POL
Selects the polarity of the End Of Transfer input (used in GDMA
slave mode only):
0 — EOT is active LOW
1 — EOT is active HIGH.
4
MASTER
Selects the DMA master/slave mode:
0 — GDMA slave mode.
1 — MDMA master mode.
3
ACK_POL
Selects the DMA acknowledgement polarity:
0 — DACK is active LOW
1 — DACK is active HIGH.
2
DREQ_POL
Selects the DMA request polarity:
0 — DREQ is active LOW
1 — DREQ is active HIGH.
1
WRITE_POL
Selects the DIOW strobe polarity:
0 — DIOW is active LOW
1 — DIOW is active HIGH.
0
READ_POL
Selects the DIOR strobe polarity:
0 — DIOR is active LOW
1 — DIOR is active HIGH.
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