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參數(shù)資料
| 型號： | 935268625518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 10/82頁 |
| 文件大小： | 1965K |
| 代理商： | 935268625518 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
18 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.2.2
Mode register (address: 0CH)
This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the
upper byte is ignored.
The Mode register controls the resume, suspend and wake-up behavior, interrupt
activity, soft reset, clock signals and SoftConnect operation.
9.2.3
Interrupt Conguration register (address: 10H)
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in Table 9. When the USB SIE receives or generates a ACK, NAK
or STALL, it will generate interrupts depending on three Debug mode bit elds:
CDBGMOD[1:0]: interrupts for the Control endpoint 0
DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7
Table 7:
Mode register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CLKAON
SNDRSU
GOSUSP
SFRESET
GLINTENA
WKUPCS
reserved
SOFTCT
Reset
0
0000
-
0
Bus reset
0
unchanged
0
-
unchanged
Access
R/W
-
R/W
Table 8:
Mode register: bit description
Bit
Symbol
Description
7
CLKAON
Clock Always On: A logic 1 indicates that the internal clocks
are always running even during ‘suspend’ state. A logic 0
switches off the internal oscillator and PLL, when they are not
needed. During ‘suspend’ state, this bit must be set to logic 0 to
meet the suspend current requirements. The clock is stopped
after a delay of approximately 2 ms, following the setting of bit
GOSUSP.
6
SNDRSU
Send Resume: Writing a logic 1 followed by a logic 0 will
generate an upstream ‘resume’ signal of 10 ms duration, after a
5 ms delay.
5
GOSUSP
Go Suspend: Writing a logic 1 followed by a logic 0 will activate
‘suspend’ mode.
4
SFRESET
Soft Reset: Writing a logic 1 followed by a logic 0 will enable a
software-initiated reset to ISP1581. A soft reset is similar to a
hardware-initiated reset (via the RESET pin).
3
GLINTENA
Global Interrupt Enable: A logic 1 enables all interrupts.
Individual interrupts can be masked OFF by clearing the
corresponding bits in the Interrupt Enable register. Bus reset
value: unchanged.
2
WKUPCS
Wake-up on Chip Select: A logic 1 enables remote wake-up
via a LOW level on input CS.
1
-
reserved; must write logic 0
0
SOFTCT
SoftConnect: A logic 1 enables the connection of the 1.5 k
pull-up resistor on pin RPU to the D
+ line. Bus reset value:
unchanged.
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