參數(shù)資料
型號： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 20/82頁
文件大?。?/td> 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
27 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.4 DMA registers
Two types of Generic DMA transfer and three types of IDE-specied transfer can be
done by writing the proper opcode in the DMA Command Register. The control bits
are given in Table 26 (Generic DMA transfers) and Table 27 (IDE-specied transfers).
GDMA read/write (opcode = 00H/01H) — Generic DMA Slave mode; Depending on
the MODE[1:0] bit set in the DMA conguration register, either the DACK signal or the
DIOR/DIOW signals are used to strobe the data. These signals are driven by the
external DMA Controller.
GDMA slave mode can operate in either counter mode or EOT only mode.
In counter mode, the DIS_XFER_CNT bit in the DMA conguration register must be
set to logic 0. The DMA transfer counter register must be programmed before any
DMA command is issued. The DMA transfer counter is set by writing from the LSByte
to the MSByte (address: 34H to 37H). The DMA transfer count is updated internally
only after the MSByte has been written. Once the DMA transfer is started, the transfer
counter starts decrementing and upon reaching ‘0’, the DMA_XFER_OK bit is set
and an interrupt is generated by the ISP1581. If the DMA master wants to terminate
the DMA transfer, it can issue an EOT signal to the ISP1581. This EOT signal
overrides the transfer counter and can terminate the DMA transfer at any time.
In the EOT only mode, DIS_XFER_CNT has to be set to logic 1. Although the DMA
transfer counter can still be programmed, it will not have any effect on the DMA
transfer. DMA transfer will start once the DMA command is issued. Any of the
following three ways will terminate this DMA transfer:
Detecting an external EOT
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA.
There are basically 3 interrupts programmable to differentiate the method of DMA
termination; namely, the INT_EOT, EXT_EOT and the DMA_XFER_OK bits in the
DMA Interrupt Reason register. Refer to Table 53 for details.
MDMA (Master) read/write (opcode = 06H/07H) — Generic DMA Master mode;
Depending on the MODE[1:0] bit set in the DMA conguration register, either the
DACK signal or the DIOR/DIOW signals are used to strobe the data. these signals
are driven by the ISP1581.
In the Master mode, BURST[2:0],DIS_XFER_CNT in the DMA conguration register
and the external EOT signal are not applicable. DMA transfer counter is always
enabled and the DMA_XFER_OK bit is set to ‘1’ once the counter reaches ‘0’.
PIO read/write (opcode = 04H/05H) — PIO mode for IDE transfers; the specication
of this mode can be obtained from the
ATA Specication Rev. 4. DIOR and DIOW are
used as data strobes, IORDY can be used by the device to extend the PIO cycle.
MDMA read/write (opcode = 06H/07H) — Multi word DMA mode for IDE transfers;
the specication of this mode can be obtained from the
ATA Specication Rev. 4.
DIOR and DIOW are used as data strobes, while DREQ and DACK serve as
handshake signals.
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