參數(shù)資料
型號(hào)： 935268625518
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 16/82頁(yè)
文件大?。?/td> 1965K
代理商： 935268625518
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
23 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.3.3
Data Port register (address: 20H)
This 2-byte register provides direct access for a microcontroller to the FIFO of the
indexed endpoint. In case of an 8-bit bus the upper byte is not used. The bit allocation
is shown in Table 19.
Device to host (IN endpoint): After each write action an internal counter is
auto-incremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next
location in the TX FIFO. When all bytes have been written (FIFO byte count =
endpoint MaxPacketSize), the buffer is validated automatically. The data packet will
then be sent on the next IN token. When it is necessary to validate the endpoint
whose byte count is less than the MaxPacketSize, it can be done via the control
function register (bit VENDP).
Host to device (OUT endpoint): After each read action an internal counter is
auto-decremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next
location in the RX FIFO. When all bytes have been read, the buffer contents are
cleared automatically. A new data packet can then be received on the next OUT
token. The buffer contents can also be cleared via the Control Function register (bit
CLBUF), when it is necessary to forcefully clear the contents.
Table 18:
Control Function register: bit description
Bit
Symbol
Description
7 to 5
-
reserved.
4
CLBUF
Clear Buffer: A logic 1 clears the RX buffer of the indexed
endpoint; the TX buffer is not affected. The RX buffer is cleared
automatically once the endpoint is read completely. This bit is
set only when it is necessary to forcefully clear the buffer.
3
VENDP
Validate Endpoint: A logic 1 validates the data in the TX FIFO
of an IN endpoint for sending on the next IN token. In general,
the endpoint is validated automatically when its FIFO byte count
has reached the endpoint MaxPacketSize. This bit is set only
when it is necessary to validate the endpoint with the FIFO byte
count which is below the Endpoint MaxPacketSize.
2
-
reserved
1
STATUS
Status Acknowledge: This bit controls the generation of ACK
or NAK during the status stage of a SETUP transfer. It is
automatically cleared upon completion of the status stage and
upon receiving a SETUP token:
0 — sends NAK
1 — sends empty packet following IN token (host-to-device) or
ACK following OUT token (device-to-host).
0
STALL
Stall Endpoint: A logic 1 stalls the indexed endpoint. This bit is
not applicable for isochronous transfers.
Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit
about the stalled endpoint because the internal logic picks up
from where it is stalled. Therefore, the Data Toggle bit must be
reset by disabling and re-enabling the corresponding endpoint
(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type
register) to reset the PID.
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