參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 89/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
89
3.7.16.
SSTS—Secondary PCI-PCI Status Register (Device 1)
Address Offset:
1E-1Fh
Default Value:
02A0h
Access:
Read Only, Read/Write Clear
Size:
16 bits
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary
side (i.e. PCI1/AGP side) of the “virtual” PCI-PCI bridge embedded within GMCH2-M.
15
14
13
12
11
10
9
8
Det. Parity
Error
Rec Sys
Error
(HW=0)
Rec
Master
Abort
Rec
Target
Abort
Sig Target
Abort
(HW=0)
DEVSEL Timing
(HW=01b; medium)
Data
Parity Det.
(HW=0)
7
6
5
4
0
FB2B
(HW=1)
Reserved
66/60 MHz
Cap
(HW=1)
Reserved
Bit
Descriptions
15
Detected Parity Error (DPE1)
.
This bit is set to a 1 to indicate GMCH2-M’s detection of a parity error in the address or data phase of
PCI1/AGP bus transactions.
Software sets DPE1 to 0 by writing a 1 to this bit.
Note
that the function of this bit is not affected by the PERRE1 bit. Also note that PERR# is not
implemented in the GMCH2-M.
14
Received System Error (SSE1)
. This bit is hardwired to 0 since the GMCH2-M does not have an
SERR# signal pin.
13
Received Master Abort Status (RMAS1)
.
This bit is set to 1 when the GMCH2-M terminates a Host-to-PCI1/AGP with an unexpected master
abort.
Software resets this bit to 0 by writing a 1 to it.
12
Received Target Abort Status (RTAS1)
.
When a GMCH2-M initiated transaction on PCI1/AGP is terminated with a target abort, RTAS1 is set to
1.
Software resets RTAS1 to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS1).
STAS1 is hardwired to a 0, since the GMCH2-M does not
generate target abort on PCI1/AGP.
10:9
DEVSEL# Timing (DEVT1)
. This 2-bit field indicates the timing of the DEVSEL# signal when the
GMCH2-M responds as a target on PCI1/AGP, and is hard-wired to the value
01b (medium)
to indicate
the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Data Parity Detected (DPD1). Hardwired to 0.
GMCH2-M does not implement G_PERR# function.
However, data parity errors are still detected and reported using SERR hub interface special cycles (if
enabled by SERRE1 and the BCTRL register, bit 0).
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