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| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 26/163頁 |
| 文件大小： | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
26
Datasheet
2.3.5.
AGP FRAME# Signals
Signal Name
Type
Description
GFRAME#
I/O
s/t/s
AGP
FRAME:
During PIPE# and SBA Operation:
Not used by AGP SBA and PIPE# operation.
During FRAME# Operation:
GFRAME# is an output when the GMCH2-M acts as
an initiator on the AGP Interface. GFRAME# is asserted by the GMCH2-M to
indicate the beginning and duration of an access. GFRAME# is an input when the
GMCH2-M acts as a FRAME# based AGP target. As a FRAME# based AGP target,
the GMCH2-M latches the C/BE[3:0]# and the AD[31:0] signals on the first clock
edge on which it samples FRAME# active.
GIRDY#
I/O
s/t/s
AGP
Initiator Ready:
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
GIRDY# indicates the AGP compliant master is ready to provide
all
write data for
the current transaction. Once IRDY# is asserted for a write operation, the master is
not allowed to insert wait states. The assertion of IRDY# for reads indicates that the
master is ready to transfer to a subsequent block (32 bytes) of read data. The
master is
never
allowed to insert a wait state during the initial data transfer (32
bytes) of a read transaction. However, it may insert wait states after each 32 byte
block is transferred. (There is no relationship between GFRAME# and GIRDY# for
AGP transactions.)
GTRDY#
I/O
s/t/s
AGP
Target Ready:
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
GTRDY# indicates the AGP compliant target is ready to provide read data for the
entire transaction (when the transfer size is less than or equal to 32 bytes). In write
case, it is ready to transfer the initial or subsequent block (32 bytes) of data when
the transfer size is greater than 32 bytes. The target is allowed to insert wait states
at the end of each block data transfer(32 bytes). Each 32-byte block is transferred
on both read and write transactions.
GSTOP#
I/O
s/t/s
AGP
Stop
:
During PIPE# and SBA Operation:This signal is not used for PIPE# or SBA
operation.
During FRAME# Operation: STOP# is an input when the GMCH2-M acts as a
FRAME# based AGP initiator and an output when the GMCH2-M acts as a
FRAME# based AGP target. STOP# is used for disconnect, retry, and abort
sequences on the AGP interface.
GDEVSEL#
I/O
s/t/s
AGP
Device Select:
During PIPE# and SBA Operation:This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation: GDEVSEL#, when asserted, indicates that a FRAME#
based AGP target device has decoded its address as the target of the current
access. The GMCH2-M asserts GDEVSEL# based on the SDRAM address range
being accessed by a PCI initiator. As an input it indicates whether any device on the
bus has been selected.
GREQ#
I
AGP
Request
:
During SBA Operation: This signal is not used during SBA operation.
During PIPE# and FRAME# Operation: GREQ#, when asserted, indicates that a
FRAME# or PIPE# based AGP master is requesting use of the AGP interface.
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