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| 型號(hào)： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 117/163頁(yè) |
| 文件大小： | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
117
4.3.1.3.
HSEG (High Segment)
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM-
mode processor accesses to enabled HSEG are considered invalid are terminated immediately on the
FSB. The exception to this is non-SMM-mode Write Back cycles. They are remapped to SMM space to
maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is not accessible.
4.3.1.3.1. TSEG (Top of Memory Segment)
TSEG can be up to 1MB in size and is at the top of memory (TOM). SMM-mode processor accesses to
enabled TSEG access the physical DRAM at the same address. Non-SMM-mode processor accesses to
enabled TSEG are considered invalid and are terminated immediately on the FSB. The exception is non-
SMM-mode Write Back cycles. They are directed to the physical SMM space to maintain cache
coherency. AGP and Hub interface originated cycles to enabled SMM memory space are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the
extended SMRAM space is enabled, non-SMM processor accesses and all other accesses in this range
are forwarded to the hub interface. When SMM is enabled the amount of memory available to the
system is equal to the amount of physical DRAM minus the value in the TSEG register.
4.3.2.
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main DRAM to 4 GB (top of physical memory space supported by the
GMCH2-M) is normally mapped via the hub interface to PCI. There are two exceptions to this rule:
Internal graphics configuration (GFX)
Addresses decoded to the Local Memory Range are forwarded to the GFX
Addresses decoded to the Memory Mapped Range of the internal graphics device (GFX) are
forwarded to the GFX
AGP configuration
Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT, PMBASE, and
PMLIMIT registers are mapped to AGP.
Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE registers
are mapped to the main DRAM.
There are two sub-ranges within the PCI Memory address range defined as APIC Configuration Space
and High BIOS Address Range. As an internal graphics device, the Local Memory Range and the
Memory Mapped Range of the internal Graphics Device
MUST NOT
overlap with these two ranges.
Similarly, as an AGP device, the AGP memory window and Graphics Aperture Window
MUST NOT
overlap with these two ranges. These ranges are described in detail in the following sections.
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