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| 型號(hào)： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 61/163頁 |
| 文件大小： | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
61
Bit
Description
5:4
Upper SMM Select (USMM).
This field is used to enable/disable the various SMM memory ranges
above 1 MB. TSEG is a block of memory (“Stolen” from Main Memory at [TOM-Size]: [TOM]) that is
only accessable by the processor and only while operating in SMM mode. HSEG is a Remap of the
AB segment at FEEA0000: FEEBFFFF. Both of these areas, when enabled, are usable as SMM
RAM.
00 = TSEG and HSEG are both Disabled
01 = TSEG is Disabled, HSEG is Conditionally Enabled
10 = TSEG is Enabled as 512 KB and HSEG is Conditionally Enabled
11 = TSEG is Enabled as 1 MB and HSEG is Conditionally Enabled
Note:
Non-SMM Operations (SMM processor accesses and all other access) that use these address
ranges are forwarded to the hub interface.
Once D_LCK is set, these bits becomes read only.
HSEG is ONLY enabled if LSMM = 00.
3:2
Lower SMM Select (LSMM).
This field controls the definition of the A&B segment SMM space
00 = AB segment Disabled (no one can write to it).
01 = AB segment Enabled as General System RAM (anyone can write to it).
10 = AB segment Enabled as SMM Code RAM Shadow. Only SMM Code Reads can access DRAM
in the AB segment (processor code reads only). SMM Data operations and all Non-SMM Operations
go to either the internal graphics device or are broadcast on the hub interface.
11 = AB segment Enabled as SMM RAM. All SMM operations to the AB segment are serviced by
DRAM, all Non-SMM Operations go to either the internal Graphics Device or are broadcast on the
hub interface (processor SMM Read/Write can access SMM space).
When D_LCK is set bit 3 becomes Read Only, and bit 2 is Writable ONLY if bit 3 is a “1”.
When bit 3 is set only the processor can access it.
1
SMM Space Locked (D_LCK):
When D_LCK is set to 1 then D_LCK, GMS, USMM, and the most
significant bit of LSMM become read only. D_LCK can be set to 1 via a normal configuration space
write but can only be cleared by a reset. The combination of D_LCK and LSMM provide convenience
with security. The BIOS can use LSMM=01 to initialize SMM space and then use D_LCK to “l(fā)ock
down” SMM space in the future so that no application software (or BIOS itself) can violate the
integrity of SMM space, even if the program has knowledge of the LSMM function. This bit also
Locks the DRP and DRP2 registers.
0
E_SMRAM_ERR (E_SMERR):
This bit is set when processor accesses the defined memory ranges
in Extended SMRAM (HSEG or TSEG) while not in SMM mode. It is software’s responsibility to clear
this bit. The software must write a 1 to this bit to clear it This bit is Not set for the case of an Explicit
Write Back operation.
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