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參數(shù)資料
| 型號(hào)： | 668-0003-C |
| 廠商： | Rabbit Semiconductor |
| 文件頁數(shù)： | 45/228頁 |
| 文件大小： | 0K |
| 描述： | IC CPU RABBIT2000 30MHZ 100PQFP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Rabbit 2000 |
| 處理器類型： | Rabbit 2000 8-位 |
| 速度： | 30MHz |
| 電壓： | 2.7V，3V，3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 316-1004 668-0003 |
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12.7.5.2 Parity, Extra Stop Bits with 8 Data Bit Characters
In order to receive parity with 8 data bits, a check is made on each character for a 9th bit
low. The 9th bit, or parity bit, is low if bit 6 of the serial port status register is set to a "1"
after the character is received. If the 9th bit is not a zero, then the serial port treats it as an
extra stop bit. So if the 9th bit low flag is not set, it should be assumed that the parity bit is
a "1."
No special precautions are necessary to receive extra stop bits, nor does the serial port
check for stop bits beyond one. If the first stop bit is missing, it is treated as a 9th (or 8th)
bit low and will be received as a 9-bit (8-bit) character.
Sending a 9th bit or an extra stop bit is easier with revisions A–C of the Rabbit 2000 chip,
which have a long stop register as described in Section B.2.3. It was more difficult to
transmit an extra stop bit or a parity bit of value "1" with the original Rabbit 2000 chip.
The difficulty arose because there is no one solution that applies to every case, although
there is a solution for every case. To send an extra stop bit or parity bit of value "1" using
the original Rabbit 2000 chip, it is necessary to delay sending the next character so that the
stop bit will be extended to a length of at least 2 baud times. In order to delay the next
character by an additional baud time, the program has to wait for the transmitter idle inter-
rupt, which takes place after the data register empty interrupt. The data register ready
interrupt request is terminated by writing to the status register. After the transmitter idle
interrupt, which takes place at the trailing edge of the stop bit, the interrupt routine must
not load the next character for another baud time, for example, 8.6 s at 115,200 bps or
104 s at 9600 bps. At the highest baud rates it makes sense to use a busy wait loop in the
interrupt routine to time out a baud step before loading the data register with the next char-
acter. The busy wait loop may be very brief since the delay can be partially made up from
the time used to save the registers on entry to the interrupt and the time used in fetching
the next character to be sent from the transmit buffer. Of course the busy wait loop runs on
the processor clock, which is subject to being throttled up and down, so the loop count
must be coordinated with the current processor speed.
A busy wait loop can still be used at slower baud rates, but then there will be a deleterious
effect on the interrupt latency unless interrupts are re-enabled in the interrupt routine. This
can certainly be done provided that the receiver and transmitter interrupts are properly dis-
patched to separate routines because the receiver and transmitter interrupts share the same
interrupt vector. In addition, when interrupts are re-enabled in the interrupt routine, there
must be coordination with the real-time kernel or the operating system (if there is one).
This coordination typically involves a nesting count of interrupt routines that much be
adjusted by each interrupt routine that re-enables interrupts before it returns. If a busy wait
loop is used, it can be expected to consume around 10% of the processors compute time
while characters are being transmitted, since it is doing busy waiting for 1 baud out of 11
baud times for each character sent. Using the transmitter idle interrupt to request the next
character will result in gaps between characters that can be as long as the worst-case inter-
rupt latency. Most applications are not bothered by gaps between characters, but certain
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