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參數(shù)資料
| 型號(hào)： | 668-0003-C |
| 廠商： | Rabbit Semiconductor |
| 文件頁(yè)數(shù)： | 166/228頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU RABBIT2000 30MHZ 100PQFP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Rabbit 2000 |
| 處理器類型： | Rabbit 2000 8-位 |
| 速度： | 30MHz |
| 電壓： | 2.7V，3V，3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 316-1004 668-0003 |
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36
Rabbit 2000 Microprocessor User’s Manual
the same priority, this introduces interrupt latency while the next routine is waiting for the
previous routine to allow more interrupts to take place. If a number of devices have inter-
rupt service routines, and all interrupts are of the same priority, then pending interrupts
can not take place until at least the interrupt service routine in progress is finished, or at
least until it changes the interrupt priority. As a rule of thumb, Rabbit Semiconductor
usually suggests that 100 s be allowed for interrupt latency on Z180-based controllers.
This can result if, for example, there are five active interrupt routines, and each turns off
the interrupts for at most 20 s.
The intention in the Rabbit is that most interrupting devices will use priority 1 level inter-
rupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3
interrupts. Since code that runs at priority level 0 or 1 never disables level 2 and level 3
interrupts, these interrupts will take place within about 20 clocks, the length of the longest
instruction or longest sensible sequence of privileged instructions followed by an unprivi-
leged instruction. It is important that the user be careful not to overdisable interrupts in
critical code sections. The processor priority should not be raised above level 1 except in
carefully considered situations.
The effect of the processor priority on interrupts is shown in Table 3-1. The priority of the
interrupt is usually established by bits in an I/O control register associated with the hard-
ware that creates the interrupt. The 8-bit interrupt register (IP) holds the processor priority
in the least significant 2 bits. When an interrupt takes place, the IP register is shifted left 2
positions and the lower 2 bits are set to equal the priority of the interrupt that just took
place. This means that an interrupt service request (ISR) can only be interrupted by an
interrupt of higher priority (unless the priority is explicitly set lower by the programmer).
The IP register serves as a 4-word stack of 2-bit words to save and restore interrupt priori-
ties. It can be shifted right, restoring the previous priority by a special instruction (IPRES).
Since only the current processor priority and 3 previous priorities can be saved in the inter-
rupt register, instructions are also provided to PUSH and POP IP using the regular stack. A
new priority can be “pushed” into the IP register with special instructions (IPSET 0,
IPSET 1
, IPSET 2, IPSET 3).
Table 3-1. Effect of Processor Priorities on Interrupts
Processor
Priority
Effect on Interrupts
0
All interrupts, priority 1,2 and 3 take place after
execution of current non privileged instruction.
1
Only interrupts of priority 2 and 3 take place.
2
Only interrupts of priority 3 take place.
3
All interrupt are suppressed (except RST instruction).
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