參數(shù)資料
型號： 5962R9572201VQC
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40
封裝： CERAMIC, DIP-40
文件頁數(shù)： 6/29頁
文件大?。?/td> 322K
代理商： 5962R9572201VQC
14
FIGURE 4. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88)
NOTES:
59. All signals switch between VOH and VOL unless otherwise specified.
60. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
61. Cascade address is valid between first and second INTA cycle.
62. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer address is
shown for the second INTA cycle.
63. Signals at HS-82C85RH or 82C88 are shown for reference only.
64. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
65. All timing measurements are made at 1.5V unless otherwise noted.
66. Status inactive in state just prior to T4.
Waveforms (Continued)
T1
T2
T3
T4
TW
TCLSH
(SEE
TCLDX2
TCLDV
TCLAX
TCLAV
TCLMH
TDVCL
TCLML
TCHDTH
TCLMH
TCVNX
TCLAV
TCHSV
TCLSH
CLK
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD15-AD0
DEN
AMWC OR AIOWC
MWTC OR IOWC
82C88
OUTPUTS
SEE NOTES
63, 64
INTA CYCLE
AD15-AD0
(SEE NOTES 61, 62)
AD15-AD0
MCE/PDEN
DT/R
INTA
DEN
82C88 OUTPUTS
SEE NOTES 63, 64
RESERVED FOR
CASCADE ADDR
TCLAZ
TSVMCH
TCLMCH
TCVNV
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
TCVNV
TCLML
TCVNX
TCLMH
TCLDX1
TCLML
TCHSV
POINTER
INVALID ADDRESS
AD15-AD0
S2
TCHDTL
TCLMCL
NOTE 66)
HS-80C86RH
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