- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄157283 > 5962R9572201VQC (INTERSIL CORP) 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40 PDF資料下載
參數(shù)資料
| 型號： | 5962R9572201VQC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 322K |
| 代理商： | 5962R9572201VQC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
21
Halt
When a software “HALT” instruction is executed the
processor indicates that it is entering the “HALT” state in one
of two ways depending upon which mode is strapped. In
minimum mode, the processor issues one ALE with no
qualifying bus control signals. In maximum mode the
processor issues appropriate HALT status on S2, S1, S0
and the 82C88 bus controller issues one ALE. The
HS-80C86RH will not leave the “HALT” state when a local
bus “hold” is entered while in “HALT”. In this case, the
processor reissues the HALT indicator at the end of the local
bus hold. An NMl or interrupt request (when interrupts
enabled) or RESET will force the HS-80C86RH out of the
“HALT” state.
Read/Modify/Write (Semaphore)
Operations Via Lock
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the
execution of an instruction. This gives the processor the
capability of performing read/modify/write operations on
memory (via the Exchange Register With Memory
instruction, for example) without another system bus master
receiving intervening memory cycles. This is useful in
multiprocessor system congurations to accomplish “test
and set lock” operations. The LOCK signal is activated
(forced LOW) in the clock cycle following decoding of the
software “LOCK” prex instruction. It is deactivated at the
end of the last bus cycle of the instruction following the
“LOCK” prex instruction. While LOCK is active a request on
a RQ/GT pin will be recorded and then honored at the end of
the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the HS-80C86RH provides a
single software-testable input pin (TEST). This input is
utilized by executing a WAIT instruction. The single WAIT
instruction is repeatedly executed until the TEST input goes
active (LOW). The execution of WAIT does not consume bus
cycles once the queue is full.
If a local bus request occurs during WAIT execution, the
HS-80C86RH three-states all output drivers while inputs and
I/O pins are held at valid logic levels by internal bus-hold
circuits. If interrupts are enabled, the HS-80C86RH will
recognize interrupts and process them when it regains control
of the bus. The WAIT instruction is then refetched, and
reexecuted.
Basic System Timing
Typical system congurations for the processor operating in
minimum mode and in maximum mode are shown in Figures
14A and 14B, respectively. In minimum mode, the MN/MX
pin is strapped to VDD and the processor emits bus control
signals (e.g. RD, WR, etc.) directly. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 82C88 bus controller
used to generate Multibus compatible bus control signals.
Figure 11 shows the signal timing relationships.
System Timing - Minimum System
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low-going)
edge of this signal is used to latch the address information,
which is valid on the address/data bus (AD0-AD15) at this
time, into the 82C82 latches. The BHE and A0 signals
address the low, high or both bytes. From T1 to T4 the M/IO
signal indicates a memory or I/O operation. At T2, the
address is removed from the address/data bus and the bus
is held at the last valid logic state by internal bus hold
devices. The read control signal is also asserted at T2. The
read (RD) signal causes the addressed device to enable its
data bus drivers to the local bus. Some time later, valid data
will be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns the
read signal to a HIGH level, the addressed device will three-
ALE
LOCK
INTA
AD0-
FLOAT
TYPE
AD15
T1
T2
T3
T4
TI
T1
T2
T3
T4
VECTOR
FIGURE 13. INTERRUPT ACKNOWLEDGE SEQUENCE
AH
BH
CH
DH
SP
BP
SI
DI
IP
FLAGSH
CS
DS
SS
ES
AL
BL
CL
DL
FLAGSL
ACCUMULATOR
BASE
COUNT
DATA
STACK POINTER
BASE POINTER
SOURCE INDEX
DESTINATION INDEX
INSTRUCTION POINTER
STATUS FLAGS
CODE SEGMENT
DATA SEGMENT
STACK SEGMENT
EXTRA SEGMENT
AX
BX
CX
DX
TABLE 4. HS-80C86RH REGISTER MODEL
HS-80C86RH
Multibus is a trademark of Intel Corporation.
相關PDF資料 |
PDF描述 |
|---|---|
| 5962R9662801VYX | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, CDFP16 |
| 59630-1-T-03-D | MAGNETIC FIELD SENSOR-HALL EFFECT, ROUND |
| 59630-1-T-03-F | MAGNETIC FIELD SENSOR-HALL EFFECT, ROUND |
| 59630-1-T-05-A | MAGNETIC FIELD SENSOR-HALL EFFECT, ROUND |
| 59630-1-T-05-F | MAGNETIC FIELD SENSOR-HALL EFFECT, ROUND |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962R9572701VXC | 制造商:Harris Corporation 功能描述: |
| 5962R9575701VXC | 制造商:Intersil Corporation 功能描述:Counter, Up/Down, 4 Bit Binary, 16 Pin, Ceramic, Flat Pack |
| 5962R9578201VCC | 制造商:Harris Corporation 功能描述: |
| 5962R9581401VXC | 制造商:Harris Corporation 功能描述: |
| 5962R9583301VFA | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。