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參數(shù)資料
| 型號： | μPD789217Y |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8 位單片微控制器) |
| 中文描述： | 8位單片機微控制器（8位單片微控制器） |
| 文件頁數(shù)： | 66/144頁 |
| 文件大小： | 632K |
| 代理商： | ΜPD789217Y |
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Preliminary Product Information
66
μ
PD789216Y, 789217Y
(a) Transmission shift register 20 (TXS20)
TXS20 is a register in which transmission data is prepared. The transmission data is output from the
TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing
data to TXS20 triggers transmission.
TXS20 can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-
accessed.
A RESET input loads FFH into TXS20.
Caution
Do not write to TXS20 during transmission.
TXS20 and the reception buffer register 20 (RXB20) are mapped at the same address,
such that any attempt to read from TXS20 results in a value being read from the RXB.
(b) Reception shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once
one entire byte has been received, RXS20 feeds the reception data to the reception buffer register 20
(RXB20).
RXS20 cannot be manipulated directly by a program.
(c) Reception buffer register 20 (RXB20)
RXB20 is used to hold reception data. Once RXS20 has received one entire byte of data, it feeds that
data into RXB20.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is
fixed to 0.
RXB20 can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-
accessed.
A RESET input makes RXB20 undefined.
Caution
RXB20 and the transmission shift register 20 (TXS20) are mapped at the same address,
such that any attempt to write to RXB20 results in a value being written to TXS20.
(d) Transmission control circuit
The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to
the data in the transmission shift register 20 (TXS20), according to the setting of the asynchronous serial
interface mode register 20 (ASIM20).
(e) Reception control circuit
The reception control circuit controls reception according to the setting of the asynchronous serial
interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If
an error is detected, the asynchronous serial interface status register 20 (ASIS20) is set according to the
status of the error.
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