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參數(shù)資料
| 型號(hào)： | μPD789217Y |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8 位單片微控制器) |
| 中文描述： | 8位單片機(jī)微控制器（8位單片微控制器） |
| 文件頁(yè)數(shù)： | 106/144頁(yè) |
| 文件大?。?/td> | 632K |
| 代理商： | ΜPD789217Y |
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Preliminary Product Information
106
μ
PD789216Y, 789217Y
Table 8-1. Operation Statuses in HALT Mode
HALT mode operation status while the main
system clock is running
HALT mode operation status while the
subsystem clock is running
Item
While the subsystem
clock is running
While the subsystem
clock is not running
While the main system
clock is running
While the main system
clock is not running
Clock generator
Can operate with the main system clock.
Does not run.
CPU
Operation disabled
Port (output latch)
Remains in the state existing before the selection of HALT mode.
16-bit timer counter
(TM90)
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
8-bit timer/event counter
(TM80)
Operation enabled
Operation enabled
Note 3
8-bit timer/event counter
(TM81)
Operation enabled
Operation enabled
Note 4
8-bit timer counter
(TM82)
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
Clock timer
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
Watchdog timer
Operation enabled
Operation disabled
Serial interface
Operation enabled
Operation enabled
Note 5
SMB
Operation enabled
Operation enabled
Note 6
A/D converter
Operation disabled
Multiplier
Operation disabled
EEPROM
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Notes 2, 7
Low-voltage indicator
Operation enabled
Note 8
External interrupt
Operation enabled
Note 8
Notes 1.
Operation is enabled while the main system clock is selected.
2.
Operation is enabled while the subsystem clock is selected.
3.
Operation is enabled only when TI80 is selected as the count clock.
4.
Operation is enabled only when TI81 is selected as the count clock.
5.
Operation is enabled in both three-wire serial I/O and UART modes while an external clock is being
used.
6.
While in slave mode, an interrupt can be generated when an address match is found.
7.
Operation is enabled when TM80 output is selected (only when TI80 is selected for TM80) as the
count clock.
8.
Maskable interrupt that is not masked
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