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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.9 Product Outline of
μ
PD784218Y Subseries
(
μ
PD784217Y, 784218Y, 78F4218Y)
1.9.1 Features
Adds the I
2
C bus interface to the
μ
PD784218 Subseries.
Internal ROM correction
Inherits the peripheral functions of the
μ
PD78078Y Subseries
Minimum instruction execution time
160 ns (main system clock: f
XX
= 12.5-MHz operation)
61
μ
s (subsystem clock: f
XT
= 32.768-kHz operation)
Instruction set suited for control applications
Interrupt controller (4-level priority)
Vectored interrupt servicing/macro service/context switching
Standby function
HALT/STOP/IDLE mode
In the low power consumption mode: HALT/IDLE mode (subsystem clock operation)
On-chip memory: Mask ROM
256 Kbytes (
μ
PD784218Y)
192 Kbytes (
μ
PD784217Y)
Flash memory 256 Kbytes (
μ
PD78F4218Y)
RAM
12,800 bytes
I/O pins: 86
Software programmable pull-up resistors: 70 inputs
LED direct drive possible: 22 outputs
Transistor direct drive possible: 6 outputs
Timer/counter: 16-bit timer/counter
×
1 unit
8-bit timer/counter
×
6 units
Watch timer: 1 channel
Watchdog timer: 1 channel
Serial interfaces
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
CSI (3-wire serial I/O, multimaster supported I
2
C bus): 1 channel
A/D converter: 8-bit resolution
×
8 channels
D/A converter: 8-bit resolution
×
2 channels
Real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently
controlled.)
Clock frequency dividing function
Clock output function: Selectable from f
XX
, f
XX
/2, f
XX
/2
2
, f
XX
/2
3
, f
XX
/2
4
, f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
, f
XT
Buzzer output function: Selectable from f
XX
/2
10
, f
XX
/2
11
, f
XX
/2
12
, f
XX
/2
13
External access status function
Power supply voltage: V
DD
= 1.8 to 5.5 V