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126
CHAPTER 3 REGISTERS
Figure 3-7. General Register Addresses
Note
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,
0F0000H should be added to the address values shown.
The
μ
PD784915 Subseries is fixed to the LOCATION 0 instruction.
Caution R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers respectively
by setting the RSS bit of the PSW to 1, but this function should only be used when using a 78K/
III Series program.
Remark
When the register bank is switched, and it is necessary to return to the original register bank, an SEL
RBn instruction should be executed after first saving the PSW to the stack with a PUSH PSW instruction.
When returning to the original register bank, if the stack location does not change the POP PSW
instruction should be used.
When the register bank is changed by a vectored interrupt service program, etc., the PSW is automatically
saved to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so
that, if only one register bank is used in the interrupt service program, only an SEL RBn instruction need
be executed, and execution of a PUSH PSW and POP W instruction is not necessary.
Example 1.
.
PUSH PSW
SEL RB2
.
Operations in register bank 2
POP PSW
.
Operations in original register bank
2.
When the register bank is specified by a vectored interrupt service program.
INT:
SEL RB5
.
Operation in register bank 5
Automatic return to original register bank
RETI
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
FEFFH
Note
FE80H
Note
7
0 7
0
15
0
H (R15)
(FH)
D (R13)
(DH)
R11
(BH)
R9
(9H)
R7
(7H)
R5
(5H)
B (R3)
(3H)
A (R1)
(1H)
L (R14)
(EH)
E (R12)
(CH)
R10
(AH)
R8
(8H)
R6
(6H)
R4
(4H)
C (R2)
(2H)
X (R0)
(0H)
HL (RP7)
(EH)
DE (RP6)
(CH)
UP (RP5)
(AH)
VP (RP4)
(8H)
RP3
(6H)
RP2
(4H)
BC (RP1)
(2H)
AX (RP0)
(0H)
8-bit processing
16-bit processing