![](http://datasheet.mmic.net.cn/380000/-PD784928Y_datasheet_16744934/-PD784928Y_214.png)
214
CHAPTER 6 INSTRUCTION SET
(5) 16-bit data exchange instruction: XCHW
Mnemonic
Operands
Operation Code
B1
B2
B3
B4
B5
B6
B7
XCHW
rp, rp’
0 0 1 0
0 1 0 1
P
7
P
6
P
5
0
1 P
2
P
1
P
0
AX, saddrp2
0 0 0 1
1 0 1 1
←
Saddr2-offset
→
rp, saddrp2
0 0 1 1
1 0 0 1
P
7
P
6
P
5
0
1 0 0 0
←
Saddr2-offset
→
rp, saddrp1
0 0 1 1
1 0 0 1
P
7
P
6
P
5
0
1 0 0 1
←
Saddr1-offset
→
rp, sfrp
0 0 1 1
1 0 0 1
P
7
P
6
P
5
0
1 0 1 0
←
Sfr-offset
→
AX, [saddrp2]
0 0 0 0
0 1 1 1
0 0 1 0
0 1 0 1
←
Saddr2-offset
→
AX, [saddrp1]
0 0 1 1
--------------------------------------------------------------------------------
1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0
0 1 0 1
←
Saddr1-offset
→
AX, [%saddrg2]
0 0 0 0
0 1 1 1
0 0 1 1
0 1 0 1
←
Saddr2-offset
→
AX, [%saddrg1]
0 0 1 1
--------------------------------------------------------------------------------
1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 1
0 1 0 1
←
Saddr1-offset
→
AX, !addr16
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
0 1 0 0
0 1 0 1
←
Low Address
→
←
High Address
→
AX, !!addr24
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
0 1 0 1
0 1 0 1
←
High-w Address
→
←
Low Address
→
←
High Address
→
saddrp2, saddrp2’
0 0 1 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 0 0
0 1 0 0
←
Saddr2’-offset
→
←
Saddr2-offset
→
saddrp2, saddrp1
0 0 1 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 0 1
0 1 0 0
←
Saddr1-offset
→
←
Saddr2-offset
→
saddrp1, saddrp2
0 0 1 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 1 0
0 1 0 0
←
Saddr2-offset
→
←
Saddr1-offset
→
saddrp1, saddrp1’
0 0 1 0
--------------------------------------------------------------------------------
1 0 1 0
1 0 1 1
0 1 0 0
←
Saddr1’-offset
→
←
Saddr1-offset
→
AX, [TDE + byte]
0 0 0 0
0 1 1 0
0 0 0 0
0 1 0 1
←
Low Offset
→
AX, [SP + byte]
0 0 0 0
0 1 1 0
0 0 0 1
0 1 0 1
←
Low Offset
→
AX, [WHL + byte]
0 0 0 0
0 1 1 0
0 0 1 0
0 1 0 1
←
Low Offset
→
AX, [UUP + byte]
0 0 0 0
0 1 1 0
0 0 1 1
0 1 0 1
←
Low Offset
→
AX, [VVP + byte]
0 0 0 0
0 1 1 0
0 1 0 0
0 1 0 1
←
Low Offset
→
AX, imm24 [DE]
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
0 0 0 0
0 1 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
AX, imm24 [A]
0 0 0 0
--------------------------------------------------------------------------------
1 0 1 0
0 0 0 1
0 1 0 1
←
Low Offset
→
←
High Offset
→
←
High-w Offset
→
(Continued on next page)