參數(shù)資料
型號： ZPSD512B1V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 1/142頁
文件大?。?/td> 786K
代理商： ZPSD512B1V
7-1
Key Features
Programmable Peripheral
ZPSD5XX Famly
Field-Programmable Microcontroller Peripherals
J
Complete family of Field Programmable Microcontroller Peripherals enables the user to
efficiently implement a highly integrated embedded control system in a short time. The
ZPSD5XX family has a variety of functions such as ZPLDs , I/O Ports, Counter/Timers,
Interrupt Controller, Power Management, EPROM and SRAM.
J
“No Glue-Logic” user programmable interface to 8 or 16 bit microcontroller multiplexed
and non-multiplexed bus. The bus control logic can directly decode control signals
generated by 8031, 80196, 80186, 68HC11, 68HC16, 683XX, 16000, Z80, and Z8
architecture. Extended address capability up to 24 bits of address.
J
A range of ZPLD (Zero Power PLD) architectures have up to 30 macrocells, 61
inputs and 140 output product terms. Includes 3 functional ZPLDs which enable the
user to efficiently implement a variety of state machines, logic functions, address
decoding and control of the internal ZPSD5XX functional blocks .
J
The ZPLDs use a Zero Power CMOS technology that reduces the device standby
current to 5 uA typical. Unused product terms are disabled to reduce operating power.
J
Up to 40 I/O Ports that can be individually configured by the user as standard MCU I/O
ports, PLD I/O, latched address outputs and special function I/O. Two eight bit I/O ports
can be configured as Open Drain Outputs.
J
Four 16 bit Counter/Timers, that have 5 modes of operation and can be controlled by the
Peripheral PLD (PPLD) macrocells. Modes of operation are pulse, waveform, time
capture, event counting and watch dog timer (or Real Time Clock). The Counter/Timer
clock input has a prescaler that can scale the input frequency from 4 to 280.
J
Eight input priority encoded Interrupt Controller. Four interrupts are generated by the
PPLD and are user defined. The other four interrupts are generated by the
Counter/Timers Terminal Count flags. Each interrupt input can be individually masked
and configured as edge or level sensitive.
J
The ZPSD5XX family contains EPROM densities of 256 Kbit, 512 Kbit and 1 Mbit that
can be configured as 8 or 16 bit data width. The EPROM is divided into 4 equal blocks
that can be mapped to different address spaces. Access time is 70 ns which includes
address latching and Decoder PLD (DPLD) decoding. The EPROM has a low power
mode that is controlled by the CMiser-Bit.
J
The ZPSD5XX family contains a 16Kbit standby SRAM that can be configured as
8 or 16 bit data width. Access time is 70 ns which includes address latching and
Decoder PLD (DPLD) decoding. The SRAM can be used as standby storage if standby
power is supplied to the Vstby pin. Switching between V
CC
and Vstby occurs
automatically.
J
Page Logic is connected to the ZPLDs and enables address space expansion of
Microcontrollers with limited address space capability. Up to 16 pages are available.
相關PDF資料
PDF描述
ZPSD513B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD513B1V Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD501B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD501B1V Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD503B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
相關代理商/技術參數(shù)
參數(shù)描述
ZPSD513B1-C-15L 制造商:WSI 功能描述:
ZPSD602E1-15L 制造商:WSI 功能描述:
ZPSD611E1-15J 制造商:WSI 功能描述:
ZPSD611E1-15JI 制造商:WSI 功能描述:
ZPSD611E1-15L 制造商:WSI 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*