參數(shù)資料
型號： ZPSD503B1V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 89/142頁
文件大?。?/td> 786K
代理商： ZPSD503B1V
ZPSD5XX Famly
7-89
Software Load/Store Register:
Each bit in this register enables a load to the corresponding Counter/Timer from its
associated Image Register in Waveform, Pulse or WatchDog modes. The actual counts are
stored in their corresponding Image Register in event Counter or time capture modes.
Counter/Timer
Registers
(Cont.)
Software Load/Store 0 Bit:
If this bit is set to
1: Counter/Timer0 CNTR0 gets loaded from the Image
Register IMG0 or CNTR0 stores into IMG0 based on the
mode of operation
**
.
Software Load/Store 1 Bit:
If this bit is set to
1: Counter/Timer1 CNTR1 gets loaded from the Image
Register IMG1 or CNTR1 stores into IMG1 based on the
mode of operation
**
.
Software Load/Store 2 Bit:
If this bit is set to
1: Counter/Timer2 CNTR2 gets loaded from the Image
Register IMG2.
Software Load/Store 3 Bit:
If this bit is set to
1: Counter/Timer3 CNTR3 gets loaded from the Image
Register IMG3 or CNTR3 stores into IMG3 based on the
mode of operation
**
.
**
Load operation takes place in Waveform, Pulse and WatchDog mode.
Store operation takes place in Event Count and Time Capture mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
Software
Load/Store 3 Load/Store 2 Load/Store 1 Load/Store 0
Software
Software
Software
NOTE:
*
= Not used.
The Software load/store bits are automatically cleared by the served Counter.
In addition to four CTU registers, there are delay cycle and Counter/Timer status registers.
These are summarized on the following pages.
相關(guān)PDF資料
PDF描述
ZPSD511B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD511B1V Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD602(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
ZPSD601(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
ZPSD603(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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