參數(shù)資料
型號： ZPSD503B1V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 65/142頁
文件大?。?/td> 786K
代理商： ZPSD503B1V
ZPSD5XX Famly
7-65
ZPSD5XX
Counter/Timer
General Description
The ZPSD5XX contains a powerful set of four 16 bit Counter/Timers, each controlled by
either PPLD outputs, external pins or Software. The Counter/Timers aid the user in
counting external events and/or generating accurate delays. These can be operated
as Counters or Timers. In Event-count, time capture and WatchDog modes, the
Counter/Timers work as Counters, whereas in Waveform and Pulse modes they work as
Timers. All Counter/Timers are capable of generating interrupts through the On-Board
Interrupt Controller. Each of the Counter/Timers consist of a Counter/Timer Command
register, Counter/Timer Image register and Counter/Timer register. All four Counter/Timers
share a Global command register, a Software Load/Store register, a Freeze command
register and the Status register. Counter/Timer 2 can support WatchDog operations.
All Counter/Timers share a common clock input and Delay Cycle register used in scaling
down the input clock to the Counter/Timer. The maximum resolution of the Counter/Timer
is the input clock of the ZPSD5XX divided by four. The maximum input clock frequency to
the ZPSD5XX is 30 MHz. Figures 32 and 33 describe the general features of the
Counter/Timers.
Features
J
Four 16 bit Counter/Timers.
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Five modes of operation
– Waveform Mode
– Pulse Mode
– Event Counter Mode
– Time Capture Mode
– WatchDog Mode
*
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Each Counter/Timer can be controlled by an input pin, dedicated PPLD macrocell or
software.
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Each Counter/Timer has an output to the Interrupt Controller.
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The WatchDog output is routed through the PLD and can be programmed to be
output at any PLD output pin.
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Programmable input and output polarity.
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Counter/Timer can be programmed as UP or DOWN Counter, except in
WatchDog mode.
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All Counters have the operating frequency range of DC to 7.0 MHz
(i.e 143 ns maximum resolution at 7.0 MHz). Higher resolution can be achieved
by using in conjunction with the GPLD macrocells.
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High resolution Divisor unit for Counter clocking purposes.
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Can easily interface with any 8 or 16 bit Microcontroller or Microprocessor.
(
*
) Counter/Timer-2 can operate in WatchDog mode.
相關PDF資料
PDF描述
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ZPSD603(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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