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| 型號(hào)： | ZPSD503B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入） |
| 文件頁(yè)數(shù)： | 64/142頁(yè) |
| 文件大小： | 786K |
| 代理商： | ZPSD503B1 |
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ZPSD5XX Famly
7-64
Power
Management
Unit
(Cont.)
Port Configuration
Pin Status
I/O Port
Unchanged
ZPLD Output
Depend on Inputs to the ZPLD
Address Out
Undefined
Data Port
Tri-stated
Special Function Out
Depending on Status of Clock Input
Peripheral I/O
Tri-stated
Table 20. I/OPin Status During Power Down And Sleep Mode
J
Input Clock
The ZPSD5XX provides the option to turn off the clock inputs to save AC power
consumption. The clock input (CLKIN) is used as a source for driving the following
modules:
J
ZPLD Array Clock Input
J
ZPLD MacroCell Clock Flip Flop
J
APD Counter Clock
J
Counter/Timer Clock
During power down or if any of the modules are not being used the clock to these
modules should be disabled. To reduce AC power consumption, it is especially important
to disable the clock input to the ZPLDS array if it is not used as part of a logic equation.
The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK). The ZPLD
MacroCell Clock Input can be disabled by setting PMMR0 bit 6 (ZPLD RCLK). The Timer
Clock can be disabled by setting PMMR0 bit 7 (TMR CLK). The APD Counter Clock
will be disabled automatically if Power Down or Sleep Mode is entered through the APD
unit. The input buffer of the CLKIN input will be disabled if bits 5 – 7 PMMR0 are set and
the APD has overflowed.
The Counter/Timers can operate in Sleep Mode if the TMR CLK bit is low, but the power
consumption will be based on the frequency of operation (CLKIN frequency).
PLD
PLD
Access
Time
Access
Recovery
Time To
Normal
Access
Typical
Standby
Current
Consumed
Propagation
Delay
Recovery
Time To
Normal
Operation
Power
Down
Normal t
PD
(Note 1)
0
No Access
t
LVDV
40 μA
(Note 4)
Sleep
t
LVDV2
(Note 2)
t
LVDV3
(Note 3)
No Access
t
LVDV1
5 μA
(Note 5)
Table 19. Summary of ZPSD5XX Timng and Standby Current During Power Down
and Sleep Modes
NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of t
LVDV2
.
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay time of t
LVDV3
.
4. Typical current consumption assuming all clocks are disabled and ZPLD is in non-turbo mode.
5. Typical current consumption assuming all clocks are disabled.
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