參數(shù)資料
型號(hào)： ZPSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入）
文件頁數(shù)： 52/142頁
文件大小： 786K
代理商： ZPSD503B1
ZPSD5XX Famly
7-52
The ZPSD5XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and are
defined by the user in the PSDsoft Software. Figure 26 shows the organization of the
Memory Block.
EPROM
The ZPSD5XX provides three Zero Power EPROM densities: 256K bit, 512K bit or 1M bit.
The EPROM is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip
select signals (ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8
for microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured
as 16K x 16, 32K x 16 or 64K x 16. The EPROM powers up only on address changes and
consumes power for the necessary time to latch data into its output latches. It then powers
down and remains in Standby Mode.
SRAM
The SRAM has 16K bits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by the chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY)
mode. This back-up mode is invoked when the V
CC
voltage drops under the VSTBY voltage
by 0.6 V. The VSTBY voltage is connected only to the SRAM and cannot be lower than
2.7 volts. The SRAM Data Retention voltage is 2 volts. The SRAM powers up only on
address changes and consumes power for the necessary time to latch data into its output
latches. It then powers down and remains in Standby Mode.
Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB or 32KB) it is
selecting.
The following rules govern how the internal ZPSD5XX memory selects/space are defined:
J
The EPROM blocks address space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with priority
given to SRAM or I/O. The portion of EPROM which is overlapped cannot be accessed.
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
Memory
Block
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