參數(shù)資料
型號(hào)： ZPSD303
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入）
文件頁(yè)數(shù)： 31/90頁(yè)
文件大小： 491K
代理商： ZPSD303
ZPSD3XX Famly
3-31
System
Applications
In Figure 14, the ZPSD3XX is configured to interface with Intel’s 80C31, which is a 16-bit
address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order
address byte. The 80C31 uses signals RD to read from data memory and PSEN to read
from code memory. It uses WR to write into the data memory. It also uses active high reset
and ALE signals. The rest of the configuration bits as well as the unconnected signals
(not shown) are application specific and, thus, user dependent.
In Figure 15, the ZPSD3XX is configured to interface with Motorola’s 68HC11, which is a
16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order
address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes.
It uses the term AS (address strobe) for the address latch pulse. RESET is an active low
signal. The rest of the configuration bits as well as the unconnected signals (not shown) are
specific and, thus, user dependent.
Figure 14.
ZPSD3XX
Interface With
Intel’s 80C31
MICROCONTROLLER
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
22
2
1
13
3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE
TXD
RXD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
A19/CSI
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43
EA/VP
X1
X2
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AD0/A0
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
RD
WR/V
PP
BHE/PSEN
ALE
RESET
GND
ZPSD3XX
80C31
34
12
V
CC
44
0.1μF
The configuration bits for Figure 14 are:
CALE
CDATA
CADDRDAT
CRESET
0
0
1
1
COMB/SEP
CRRWR
CEDS
0 or 1 (both valid)
0
0
All other configuration bits may vary according to the application requirements.
NOTE:
RESET to the ZPSD3XX must be the output of a RESET chip or buffer.
If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the
ZPSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
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