3-19
ZPSD3XX Famly
Configuration
Bits
No.
of Bits
Function
Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output
CPBCOD
8
Port C A16–A18 or CS8–CS10
CPCF = 0, Port C pin is A16–A18
CPCF = 1, Port C pin is CS8–CS10
CPCF
3
CADLOG
(Note 16)
Port C: A16–A19 Address or Logic Input
CADLOG = 0, Port C pin or A19/CSI is logic input
CADLOG = 1, Port C pin or A19/CSI is address input
4
CMISER
1
Default: CMISER = 0
CMISER = 1, lower-power mode
Port Functions
(Cont.)
Port A in Multiplexed Address/Data Mode
The default configuration of Port A is I/O. In this mode, every pin can be set as an input or
output by writing into the respective pin’s direction flip flop (DIR FF, in Figure 5). As an
output, the pin level can be controlled by writing into the respective pin’s data flip flop
(DFF, in Figure 5). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0,
the pin is configured as an input. The controller can read the DIR FF bits by accessing the
READ DIR register; it can read the DFF bits by accessing the READ DATA register. Port A
pin levels can be read by accessing the READ PIN register. Individual pins can be
configured as CMOS or open drain outputs. Open drain pins require external pull-up
resistors. For addressing information, refer to Tables 6 and 7.
Alternatively, each bit of Port A can be configured as a low-order latched address bus bit.
The address is provided by the port address latch, which latches the address on the trailing
edge of ALE. PA0–PA7 can become A0–A7, respectively. This feature enables the user
generate low-order address bits to access external peripherals or memory that require
several low-order address lines.
Another mode of Port A, i.e., Track Mode (CPAF2 = 1) sets the entire port to track the
inputs AD0/A0–AD7/A7, depending on specific address ranges defined by the PAD’s
CSADIN, CSADOUT1, and CSADOUT2 signals. This feature lets the user interface the
microcontroller to shared external resources without requiring external buffers and
decoders. In this mode, the port is effectively a bi-directional buffer. The direction is
controlled by using the input signals ALE, RD/E or RD/E/DS, WR/V
PP
or R/W, and the
internal PAD outputs CSADOUT1, CSADOUT2 and CSADIN (see Figure 6). When
CSADOUT1 and ALE are true, the address on the input AD0/A0–AD7/A7 pins is output
through Port A. (Carefully check the generation of CSADOUT1, and ensure that it is stable
during the ALE pulse. When CSADOUT2 is active, a write operation is performed
(see note to Figure 6). The data on the input AD0/A0–AD7/A7 pins flows out through Port A.
When CSADIN and a read operation is performed (depending on the mode of the RD/E
or RD/E/DS, and WR/V
PP
or R/W pins), the data on Port A flows out through the
AD0/A0–AD7/A7 pins. In this operational mode, Port A is tri-stated when none of the
above-mentioned three conditions exist.
Table 5.
ZPSD3XX
Configuration
Bits (Cont.)
NOTES:
13. WSI's PSD Development software will guide the user to the proper configuration choice.
14. In an unprogrammed or erased part, all configuration bits are 0.
15. ZPSD30X only.
16. ZPSD3X2/3X3/3X4R only.
17. ZPSD3X1 only.
17a. Not included in ZPSD3XXV versions.
This data sheet provides a complete listing of the function of each configuration bit in all
control registers. In general, you will not need to be concerned about the details of most of
these bits. The development software will set the bits automatically using information from
your design files.