參數(shù)資料
型號(hào): Z9951AA
英文描述: NINE DISTRIBUTED-OUTPUT CLOCK DRIVER|TQFP|32PIN|PLASTIC
中文描述: 第九分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 32腳|塑料
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 49K
代理商: Z9951AA
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07084 Rev. *A
06/18/2001
Page 2 of 8
Z9951
Pin Description
PIN
8
9
30
28
26
22, 24
12, 14, 16,
18, 20
2
10
NAME
PWR
I/O
I
I
I
O
O
O
O
TYPE
PU
Description
PECL_CLK
PECL_CLK#
TCLK
QA
QB
QC(1,0)
QD(4:0)
PECL Input Clock.
PECL Input Clock.
External Test Clock Input.
Clock Output. See Frequency Table.
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Clock Outputs. See Frequency Table.
VDDC
VDDC
VDDC
VDDC
FB_IN
MR/OE#
I
I
PD
Feedback Clock Input. Connect to an output for normal operation.
Master Reset/Output Enable Input. When asserted high, resets
all of the internal flip-flops and also disables all of the outputs.
When pulled low, releases the internal flip-flops from reset and
enables all of the outputs.
PLL Enable Input. When asserted high, PLL is enabled. And
when set low, PLL is bypassed.
Reference Select Input. When high, TCLK is the reference clock
and when low, PECL clock is selected.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 1, then QA divider =
÷
4, QB:D divider =
÷
8
If SEL_ = 0, then QA divider =
÷
2, QB:D divider =
÷
4
3.3V Power Supply for Output Clock Buffers.
31
PLL_EN
I
32
REF_SEL
I
3, 4, 5, 6
SEL(A:D)
I
11, 15, 19,
23, 27
1
7, 13, 17, 21,
25, 29
PD = Internal Pull-Down, PU = Internal Pull-Up.
VDDC
VDD
VSS
3.3V Power Supply for PLL
Common Ground
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