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參數(shù)資料
| 型號： | Z9104CAB |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):8A; Peak Non Repetitive Surge Current, Itsm:100A; Gate Trigger Current Max, Igt:15uA |
| 中文描述： | 六分布式輸出時鐘驅(qū)動器| TQFP封裝| 32腳|塑料 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 69K |
| 代理商： | Z9104CAB |
Variable Delay Motherboard Clock Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07083 Rev. *A
5/07/2001
Page 5 of 8
Z9104
APPROVED PRODUCT
Buffer Characteristics for CLK25
Characteristic
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
Rise & Fall Time Between
0.8 V and 2.0 V
Output buffer Dynamic Impedance
Symbol
IOH
min
IOH
max
IOL
min
IOL
max
TRF
Min
Typ
Max
Units
mA
mA
mA
mA
nS
Conditions
Vout = VDD25 -.5V
Vout = VDD25/2
Vout = 0.4V
Vout = VDD25/2
30 pF Load
-13
-25
11
25
0.1
-
-
-
-
-
-
-
-
-
1.0
Z
O
7
10
Ohms
VDD = VDDF =3.3V
±
5%, VDD25 = 2.5 + 5%, TA = 0oC to +70oC
Output Clock Disable and Enable Timing
When each clock enable pin (SC25 through SC6) is brought to a logic low level, its related output clock (CLK25 through
CLK6) will be forced to a logic low level. All clocks maintain a valid high period on transitions from running to stopped.
The clocks transition between running and stopped by waiting for one normally occurring positive edge followed by a
negative edge of their own clock. At that point they remain low until their respective SC signal goes high. At that point the
internal logic waits 1 internally occurring cycle and the clock then begins normal output at the next naturally occurring low
to high transitioning time.
Fig. 2
Stop on next falling edge
Start on next
rising edge
CLKx
SCx
CLK
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