參數(shù)資料
型號: XRT86VL34IB
廠商: Exar Corporation
文件頁數(shù): 39/155頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 4CH 225BG
標(biāo)準(zhǔn)包裝: 84
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT86VL34
128
REV. V1.2.1
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
RxJASEL_n
R/W
0
Receive Jitter Attenuator Enable
This bit permits the user to enable or disable the Jitter Attenuator in
the Receive Path within the XRT86VL34 device.
0 = Disables the Jitter Attenuator to operate in the Receive Path
within the Receive T1 LIU Block.
1 = Enables the Jitter Attenuator to operate in the Receive Path
within the Receive T1 LIU Block.
2
TxJASEL_n
R/W
0
Transmit Jitter Attenuator Enable
This bit permits the user to enable or disable the Jitter Attenuator in
the Transmit Path within the XRT86VL34 device.
0 = Disables the Jitter Attenuator to operate in the Transmit Path
within the Transmit T1 LIU Block.
1 = Enables the Jitter Attenuator to operate in the Transmit Path
within the Transmit T1 LIU Block.
1
JABW_n
R/W
0
Jitter Attenuator Bandwidth Select:
In T1 mode, the Jitter Attenuator Bandwidth is always 3Hz, and this
bit has no effect on the Jitter Attenuator Bandwidth. The FIFOS (bit
D0 of this register) will be used to select the FIFO size, according to
the table below.
0
FIFOS_n
R/W
0
FIFO Size Select: See table of bit D1 above for the function of this
bit.
TABLE 108: LIU CHANNEL CONTROL REGISTER 1 (LIUCCR1)
HEX ADDRESS: 0X0FN1
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
1
0
1
JABW
bit D1
T1
E1
Mode
32
64
32
64
32
64
FIFO
Size
3
10
1.5
JA B-W
Hz
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