參數(shù)資料
型號: XRT86VL34IB
廠商: Exar Corporation
文件頁數(shù): 25/155頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 4CH 225BG
標準包裝: 84
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT86VL34
115
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.1
2
FCS ERR ENB
R/W
0
FCS Error Interrupt Enable
This bit enables or disables the “Received FCS Error “Interrupt
within the XRT86VL34 device. Once this interrupt is enabled, the
Receive HDLC2 Controller will generate an interrupt when it has
detected the FCS error within the incoming data link message.
0 = Disables the “Receive FCS Error” interrupt.
1 = Enables the “Receive FCS Error” interrupt.
1
RxABORT ENB
R/W
0
Receipt of Abort Sequence Interrupt Enable
This bit enables or disables the “Receipt of Abort Sequence“Inter-
rupt within the XRT86VL34 device. Once this interrupt is enabled,
the Receive HDLC2 Controller will generate an interrupt when it has
detected the Abort Sequence (i.e. a string of seven (7) consecutive
1’s) within the incoming data link channel.
0 = Disables the “Receipt of Abort Sequence” interrupt.
1 = Enables the “Receipt of Abort Sequence” interrupt.
0
RxIDLE ENB
R/W
0
Receipt of Idle Sequence Interrupt Enable
This bit enables or disables the “Receipt of Idle Sequence“Interrupt
within the XRT86VL34 device. Once this interrupt is enabled, the
Receive HDLC2 Controller will generate an interrupt when it has
detected the Idle Sequence Octet (i.e. 0x7E) within the incoming
data link channel.
0 = Disables the “Receipt of Idle Sequence” interrupt.
1 = Enables the “Receipt of Idle Sequence” interrupt.
TABLE 97: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2)
HEX ADDRESS: 0XnB17
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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