TABLE
參數(shù)資料
型號： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 10/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標準包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
102
REV. V1.2.1
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 86: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR)
HEX ADDRESS: 0XnB08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
TxSB_FULL
RUR/
WC
0
Transmit Slip buffer Full Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Full interrupt has occurred since the last read of this register.
The transmit Slip Buffer Full interrupt is declared when the transmit
slip buffer is filled. If the transmit slip buffer is full and a WRITE oper-
ation occurs, then a full frame of data will be deleted, and this inter-
rupt bit will be set to ‘1’.
0 = Indicates that the Transmit Slip Buffer Full interrupt has not
occurred since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Full interrupt has occurred
since the last read of this register.
6
TxSB_EMPT
RUR/
WC
0
Transmit Slip buffer Empty Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Empty interrupt has occurred since the last read of this regis-
ter. The transmit Slip Buffer Empty interrupt is declared when the
transmit slip buffer is emptied. If the transmit slip buffer is emptied
and a READ operation occurs, then a full frame of data will be
repeated, and this interrupt bit will be set to ‘1’.
0 = Indicates that the Transmit Slip Buffer Empty interrupt has not
occurred since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Empty interrupt has
occurred since the last read of this register.
5
TxSB_SLIP
RUR/
WC
0
Transmit Slip Buffer Slips Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Slips interrupt has occurred since the last read of this register.
The transmit Slip Buffer Slips interrupt is declared when the transmit
slip buffer is either filled or emptied. This interrupt bit will be set to ‘1’
in either one of these two conditions:
1. If the transmit slip buffer is emptied and a READ operation
occurs, then a full frame of data will be repeated, and this
interrupt bit will be set to ‘1’.
2. If the transmit slip buffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit
will be set to ‘1’.
0 = Indicates that the Transmit Slip Buffer Slips interrupt has not
occurred since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Slips interrupt has
occurred since the last read of this register.
NOTE:
Users still need to read the Transmit Slip Buffer Empty
Interrupt (bit 6 of this register) or the Transmit Slip Buffer
Full Interrupts (bit 7 of this register) to determine whether
transmit slip buffer empties or fills.
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