Rev. 1.01 10.1 Reading Figures 25 and 26 Figures 25 and 26 are linear (as opposed to logarithmic) plots. The Jitter Gain is computed" />
參數(shù)資料
型號(hào)： XRT8001IP-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 39/48頁(yè)
文件大?。?/td> 0K
描述： IC WAN CLOCK E1/E1 DUAL 18PDIP
產(chǎn)品變化通告： XRT obsolescence 05/Mar/2012
標(biāo)準(zhǔn)包裝： 41
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： 以太網(wǎng)（WAN），T1/E1
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 16.384kHz
電源電壓： 3.3 V ~ 5 V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 18-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 18-PDIP
包裝： 管件
XRT8001
44
Rev. 1.01
10.1 Reading Figures 25 and 26
Figures 25 and 26 are linear (as opposed to logarithmic)
plots. The Jitter Gain is computed via the following
equation.
Jitter
Gain
(at
Jitter
Frequency
f)
=
(Jitter_Amplitude_CLK)/(Jitter_Amplitude_FIN)
Where:
Jitter_Amplitude_FIN = The Jitter Amplitude ap-
plied to the “FIN” input (at Jitter Frequency f).
Jitter_Amplitude_CLK = The Jitter Amplitude
measured at the “CLK1” or “CLK2” output, when
“Jitter_Amplitude_FIN” is applied to the FIN input
in of the XRT8001.
Hence, the Jitter Gain is not expressed in terms of dB,
but simply a ratio of two numbers.
Wherever the Jitter Gain exceeds “1.0” in value, then,
for those “Jitter Frequencies” the XRT8001 amplifies
Jitter (e.g., the amplitude of the jitter, as it propagates
from the “FIN” input to the “CLK1” or CLK2” output,
increases).
Conversely, wherever the Jitter Gain falls below “1.0”
in value, then for those “Jitter Frequencies” the
XRT8001 attenuates jitter (e.g., the amplitude of the
jitter, as it propagates from the “FIN” input to the “CLK1”
or “CLK2” output, decreases).
Figures 25 and 26 indicate that for Jitter Frequencies,
ranging between 100Hz and 1100Hz, the XRT8001
amplifies Jitter. Further, these figures also indicate
that for Jitter Frequencies greater than 1100Hz, that
the XRT8001 attenuates Jitter.
10.2 Test Conditions for Measurements associated
with Figures 25 and 26
Power Supply voltage either 3.3V or 5.V
Input Clock Frequency = 2.048MHz
Output Clock Frequency = 2.048MHz
Input Jitter Amplitude = 0.25Upp.
Ambient Temperature = 25°C.
11.0 PCB layout guidelines for the XRT8001
Use a multi-layer circuit board with separate plane
layers for “+5V” (or 3.3V) and “Ground” .
BypasstheAnalogVDDpintogroundwitha6.9mF
“ceramic” capacitor.
Use large “vias” located close to the IC package to
ensure that Digital VDD (e.g., pins 7, 12 and 15)
and Digital Ground (e.g., pins 4, 5 and 14) have a
low inductance path to the +5V (+3.3V) and Ground
Planes, respectively.
BypasstheDigitalVDDpins(pin10)togroundwith
a 0.1mF ceramic capacitors that are located as
close as possible to the IC package.
12.0 Comparing the XRT8001 with the earlier pin-
compatible XRT8000
The XRT8001 is pin-to-pin compatible with the
XRT8000. However, there are some functional differ-
ences between these two products. These differences
are summarized below.
1) The XRT8001 can be configured to generate frequen-
cies up to 2.048MHz, 4.096MHz, 8.192MHz or
16.384MHz.
The Maximum Frequency that the XRT8000 can gen-
erate is either 2.048MHz or 1.544MHz
2) The XRT8001 can be configured to accept an E1 rate
clock signal and synthesize a T1 rate clock signal. The
XRT8001 can also synthesize an E1 rate clock signal,
when provided with a T1 rate clock signal
The XRT8000 can be configured to accept a T1 rate
clock signal (e.g., 1.544MHz) and can be easily config-
ured to synthesize an E1 rate clock signal (e.g.,
2.048MHz).
However, the XRT8000 cannot be configured to accept
an E1 rate clock signal and synthesize a T1 rate clock
signal.
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